A rail‐to‐rail low‐power latch comparator with time domain bulk‐tuned offset cancellation for low‐voltage applications

Abstract

SummaryLow‐voltage high‐precision comparators are the main building blocks of many low‐power mixed‐mode electronic devices. In this paper, a rail‐to‐rail high‐precision comparator is introduced. The proposed comparator uses 2 parallel input P‐type metal‐oxide‐semiconductor pairs with a dynamic level shifter to ensure rail‐to‐rail operation. Moreover, the proposed circuit incorporates a rail‐to‐rail offset cancellation circuit. The offset cancellation circuit works based on a time domain bulk‐tuned negative feedback loop. The proposed comparator and offset cancellation circuits are designed to work correctly when the input common mode voltage varies from rail to rail. The rail‐to‐rail scheme allows the use of the proposed comparator in nanometer technologies, where the acceptable input range is limited. The proposed circuit was simulated in a standard 180 nm complementary metal‐oxide‐semiconductor technology, and the results proved the rail‐to‐rail comparison ability in addition to the rail‐to‐rail offset cancellation function. The overall power consumption of the comparator was only increased by 11% compared with the conventional non–rail‐to‐rail approach. The maximum clock frequency of the proposed circuit is 833 MHz, which is slightly more than its counterpart at similar operation conditions.

Design of 150‐μV input‐referred voltage 1‐GHz comparison frequency dual offset cancelation comparator for pH biomarker system‐on‐chip

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“…An energy‐efficient pipelined ADC is deeply reliant on the energy‐efficient comparator 28 . So in this structure, we have designed a latch with maximum power efficiency and minimum delay of output voltage.…”

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