Low-power branch prediction techniques for VLIW architectures: a compiler-hints based approach

Monchiero, Matteo; Palermo, Gianluca; Sami, M.; Silvano, Cristina; Zaccaria, Vittorio; Zafalon, R.

doi:10.1016/j.vlsi.2004.07.012

Cited by 8 publications

(9 citation statements)

References 26 publications

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“…The significantly low branch density of 4.86% for the gsm e is due to the existence of a basic block containing more than 300 instructions. As previous BTB filtering techniques [1,2,3] have to access the BTB for all branch instructions, these branch density values actually reflect the upper bound of power reduction that can be achieved by previous work. The second column, denoted as Taken%, lists the percentage of taken branches out of the total number of executed instructions.…”

Section: Simulation Resultsmentioning

confidence: 67%

“…An application customizable branch target buffer (ACBTB) is proposed in [2], which records for each branch the ACBTB indices corresponding to the two possible subsequent branches to determine in advance the ACBTB entry of the upcoming branch. Another compiler technique is proposed in [3] to filter BTB accesses in VLIW architectures. To inform the processor that a branch is forthcoming, a configurable hint instruction that anticipates the branch address is inserted into the program.…”

Section: Previous Workmentioning

confidence: 99%

“…As shown in Figure 1b, if the calculated branch address indicates that the next branch is not forthcoming, an access to the dynamic branch predictor can be completed at first, enabling the BTB to be only looked up if the branch is predicted to be taken. In fact, the ability to eliminate BTB accesses for non-taken branches constitutes the most significant advantage of our framework over previous BTB filtering techniques [1,2,3].…”

Section: Technical Motivationmentioning

confidence: 99%

See 2 more Smart Citations

Power efficient branch prediction through early identification of branch addresses

Yang

Orailoğlu

2006

Proceedings of the 2006 International Conference on Compilers, Architecture and Synthesis for Embedded Systems

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Section: Simulation Resultsmentioning

confidence: 67%

Section: Previous Workmentioning

confidence: 99%

Section: Technical Motivationmentioning

confidence: 99%

See 1 more Smart Citation

Power efficient branch prediction through early identification of branch addresses

Yang

Orailoğlu

2006

Proceedings of the 2006 International Conference on Compilers, Architecture and Synthesis for Embedded Systems

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“…Chaver et al [16] used profiling information to adapt the predictor hardware on the fly. Monchiero et al [17] proposed to use compiler-inserted hint instructions to inform the VLIW processor that a branch is coming. If the target is known, the branch can be taken without penalty.…”

Section: Related Workmentioning

confidence: 99%

Extending the Cell SPE with Energy Efficient Branch Prediction

Briejer

Meenderinck

Juurlink

2010

Euro-Par 2010 - Parallel Processing

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Abstract. Energy-efficient dynamic branch predictors are proposed for the Cell SPE, which normally depends on compiler-inserted hint instructions to predict branches. All designed schemes use a Branch Target Buffer (BTB) to store the branch target address and the prediction, which is computed using a bimodal counter. One prediction scheme predecodes instructions when they are fetched from the local store and accesses the BTB only for branch instructions, thereby saving power compared to conventional dynamic predictors that access the BTB for every instruction. In addition, several ways to leverage the existing hint instructions for the dynamic branch predictor are studied. We also introduce branch warning instructions which initiate branch prediction before the actual branch instruction is fetched. They allow fetching the instructions starting at the branch target and thus completely remove the branch penalty for correctly predicted branches. For a 256-entry BTB, a speedup of up to 18.8% is achieved. The power consumption of the branch prediction schemes is estimated at 1% or less of the total power dissipation of the SPE and the average energy-delay product is reduced by up to 6.2%.

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“…Dynamic branch prediction has not been a favorable choice in the generic VLIW architecture because of its hardware cost and additional power consumption [13,14]. In fact, a dynamic branch predictor itself is a cache and accessed every cycle of the execution, consuming up to 10% of the processor power [13,14]. However, in the clustered loop buffer VLIW architecture, the major consideration is on loop buffer codes with which almost 70% of an application's execution time is spent.…”

Section: Introductionmentioning

confidence: 99%

Branch Prediction and Power Reduction Techniques in the Clustered Loop Buffer VLIW Architecture

Dankanikote

Park

Chu

2007

2007 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing

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The clustered loop buffer VLIW processor has been developed to enhance the performance of multimedia applications in which loop intensive codes are used. In this paper, we employ a dynamic branch predictor in the clustered loop buffer VLIW architecture to handle branch instructions in loop-rich codes, such as multimedia applications, via dynamic speculation. To reduce the energy consumption we map two power reduction techniques, which are hint instruction method and pipeline gating method, on the architecture and analyze their performances using MediaBench applications. In our experiment, we observed that the hint instruction method helps reducing the dynamic branch predictor usage for all the applications tested, by at least 70%. The pipeline gating method was observed to be beneficial to only a subset of the applications with up to 20% of savings.

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Low-power branch prediction techniques for VLIW architectures: a compiler-hints based approach

Cited by 8 publications

References 26 publications

Power efficient branch prediction through early identification of branch addresses

Power efficient branch prediction through early identification of branch addresses

Extending the Cell SPE with Energy Efficient Branch Prediction

Branch Prediction and Power Reduction Techniques in the Clustered Loop Buffer VLIW Architecture

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