No abstract
Advances in semiconductor technologies have placed MPSoCs center stage as a standard architecture for embedded applications of ever increasing complexity. Because of real-time constraints, applications are usually statically parallelized and scheduled onto the target MPSoC so as to obtain predictable worst-case performance. However, both technology scaling trends and resource competition among applications have led to variations in the availability of resources during execution, thus questioning the dynamic viability of the initial static schedules. To eliminate this problem, in this paper we propose to statically generate a compact schedule with predictable response to various resource availability constraints. Such schedules are generated by adhering to a novel band structure, capable of spawning dynamically a regular reassignment upon resource variations. Through incorporating several soft constraints into the original scheduling heuristic, the proposed technique can furthermore exploit the inherent timing slack between dependent tasks, thus retaining the spatial and temporal locality of the original schedule. The efficacy of the proposed technique is confirmed by incorporating it into a widely adopted list scheduling heuristic, and experimentally verifying it in the context of single processor deallocations.
Outsourcing of the various aspects of IC design and fabri cation flow strongl y questions the classic assumption that "hardware is trustworth y ". Multiprocessor S y stem-on-Chip (MPSoC) platforms face some of the most demanding securit y concerns, as they process, store, and communicate sensitive information using third-part y intellectual property (3PIP) cores that ma y be untrustworth y . The complexit y of an MPSoC makes it expensive and time consuming to full y anal y ze and test it during the design stage. Consequently, the trustworthiness of the 3PIP components cannot be ensured. To protect MPSoCs against malicious modifications, we propose to incorporate trojan toleration into MPSoC platforms b y revising the task scheduling step of the MPSoC design process. We impose a set of securit y -driven diversit y constraints into the scheduling process, enabling the s y stem to detect the presence of malicious modifications or to mute their effects during application execution. Furthermore, we pose the securit y -constrained MPSoC task scheduling as a multi-dimensional optimization problem, and propose a set of heuristics to ensure that the introduced securit y constraints can be fulfilled with minimum performance and hardware overhead.
Hybrid cache architectures have been proposed to mitigate the increasing on-chip power dissipation through the exploitation of the emerging non-volatile memories (NVMs). To overcome the high energy and long latency associated with write operations of NVMs, a small SRAM is typically incorporated into the hybrid cache for accommodating write-intensive cache blocks. How to efficiently manage this SRAM and manipulate the write operations are crucial to the performance of the hybrid cache. In this paper, we first present our observation that the intensity of write operations on different cache sets is usually non-uniform for real applications, such as multimedia, multi-programmed, multithreaded applications. The previously proposed hybrid cache schemes can not efficiently and symmetrically utilize the small SRAM to accommodate such widely-existing non-uniform writes on cache sets.Based on this observation, we propose a novel hybrid cache design, Dual Associative Hybrid Cache (denoted as DAHYC), as well as the corresponding cache management policy. By organizing the SRAM blocks in the hybrid cache as a semi-independent set-associative cache, several hybrid cache sets can efficiently share and cooperatively utilize their SRAM blocks, instead of exclusively utilizing the SRAM blocks in each cache set in previous hybrid cache schemes, to boost power-efficiency. Through prudently manipulating the locality information of SRAM blocks in both the NVM sets and the SRAM sets, the proposed cache management policy also delivers high-performance. Experimental results show that, compared with previous works, the DAHYC can reduce the dynamic power of the hybrid cache by 24.8% on average and up to 54% for SPEC2000 INT benchmarks, while at the same time improving the performance of the hybrid cache by 1.16% on average.
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