Exploiting set-level write non-uniformity for energy-efficient NVM-based hybrid cache

Abstract

Hybrid cache architectures have been proposed to mitigate the increasing on-chip power dissipation through the exploitation of the emerging non-volatile memories (NVMs). To overcome the high energy and long latency associated with write operations of NVMs, a small SRAM is typically incorporated into the hybrid cache for accommodating write-intensive cache blocks. How to efficiently manage this SRAM and manipulate the write operations are crucial to the performance of the hybrid cache. In this paper, we first present our observation that the intensity of write operations on different cache sets is usually non-uniform for real applications, such as multimedia, multi-programmed, multithreaded applications. The previously proposed hybrid cache schemes can not efficiently and symmetrically utilize the small SRAM to accommodate such widely-existing non-uniform writes on cache sets.Based on this observation, we propose a novel hybrid cache design, Dual Associative Hybrid Cache (denoted as DAHYC), as well as the corresponding cache management policy. By organizing the SRAM blocks in the hybrid cache as a semi-independent set-associative cache, several hybrid cache sets can efficiently share and cooperatively utilize their SRAM blocks, instead of exclusively utilizing the SRAM blocks in each cache set in previous hybrid cache schemes, to boost power-efficiency. Through prudently manipulating the locality information of SRAM blocks in both the NVM sets and the SRAM sets, the proposed cache management policy also delivers high-performance. Experimental results show that, compared with previous works, the DAHYC can reduce the dynamic power of the hybrid cache by 24.8% on average and up to 54% for SPEC2000 INT benchmarks, while at the same time improving the performance of the hybrid cache by 1.16% on average.

Prediction Hybrid Cache: An Energy-Efficient STT-RAM Cache Architecture

“…One common approach to this is to allocate blocks that are loaded due to write (or store) misses 7 into the SRAM region and other blocks to the STT-RAM region [1], [2], [6], [7]. The major weakness of it is that it has a high possibility to miss many write-intensive blocks due to its simplicity.…”

“…More specifically, many researchers proposed to determine the region where to place a block based only on the type of operations (read/write) [1], [2], [6], [7], which is not good enough to identify write-intensive blocks accurately. Recent studies proposed compilation techniques to identify write-intensive data at compilation time and to provide the information as a hint to the runtime system [8], [9], [10].…”

“…Utilizing SRAM/STT-RAM hybrid caches [1], [2], [3], [4], [5], [6], [7] is one of the most common approaches to compensate the effect of inefficient write operations of non-volatile memory. Since write energy of SRAM is much smaller than that of typical non-volatile memory, it helps to reduce write activities in non-volatile memory thereby reducing dynamic energy consumption.…”

Adaptive replacement policy for hybrid cache architecture

“…As some researchers have appointed [5], write intensity varies across sets, thus, we check the relation between the change of write counts of NVM and the rate of the write intensive blocks for each set. Fig.…”

“…Hybrid cache architecture (HCA) has been proposed to decrease the number of write operations of NVM [4,5,6]. HCA is basically composed of NVM, but it also has a small amount of SRAM to reduce write pressure on NVM.…”