Prediction Hybrid Cache: An Energy-Efficient STT-RAM Cache Architecture

Abstract

Spin-transfer torque RAM (STT-RAM) has emerged as an energy-efficient and high-density alternative to SRAM for large on-chip caches. However, its high write energy has been considered as a serious drawback. Hybrid caches mitigate this problem by incorporating a small SRAM cache for write-intensive data along with an STT-RAM cache. In such architectures, choosing cache blocks to be placed into the SRAM cache is the key to their energy efficiency. This paper proposes a new hybrid cache architecture called prediction hybrid cache. The key idea is to predict write intensity of cache blocks at the time of cache misses and determine block placement based on the prediction. We design a write intensity predictor that realize the idea by exploiting a correlation between write intensity of blocks and memory access instructions that incur cache misses of those blocks. It includes a mechanism to dynamically adapt the predictor to application characteristics. We also design a hybrid cache architecture in which write-intensive blocks identified by the predictor are placed into the SRAM region. Evaluations show that our scheme reduces energy consumption of hybrid caches by 28% (31%) on average compared to the existing hybrid cache architecture in a single-core (quad-core) system.

A Review of Techniques for Optimizing Cache Energy Efficiency

“…In [12] reduce the cache access time that also helpful in reducing the energy. In the [13] presents a technique for heavy amount of cache set-associative that use the bloom [7] hypothesis base architecture [8] TLB Index-Based [9] Way-Halting cache filters [10] Reduce the number of cache access Selective cache way [11] reduce the access time [12] set-associative cache use the bloom filters [13] bloom filter [14] PS-cache architecture [15] Hybrid cache architecture data-aware hybrid STT-RAM/SRAM cache architecture [19] NVM [20] prediction hybrid architecture [23] Other technique MultiCopy Cache (MC2) architecture [22] Filters that decrease the dynamic power by eliminating those cache ways that are not have the requested data as the bloom filters. [14] Presents another bloom filter that reduces the complexity and also reduces the access ways.…”

A Survey of Emerging Architectural Techniques for Improving Cache Energy Consumption

“…Some techniques aim to reduce the number of active ways accessed in each cache access to the number of ways halted in case of a miss prediction using software or hardware. Other techniques reconfigure cache using computer software [71] while some techniques predict the program behaviour [55,1,59]. Some techniques deal with instructions in the cache [16,35].…”

Low-power heterogeneous uncore architecture for future 3D chip-multiprocessors

“…For instance, SRAM is a low-density technology that dissipates high leakage power [29,30]; DRAM requires refresh operations to preserve its data integrity. To address these issues, the use of emerging nonvolatile memory (NVM) technologies for on-chip memories have attracted much attention [20][21][22][23][24]29]. To address these issues, the use of emerging nonvolatile memory (NVM) technologies for on-chip memories have attracted much attention [20][21][22][23][24]29].…”

“…While most of the previous studies on multicore processors have focused on the design of on-chip interconnection networks [12][13][14][15][16][17][18][19] and memory architectures [20][21][22][23][24][25][26][27][28] separately, in this study, to achieve power efficiency, we explore the role of uncore components on CMP performance and power behavior.…”

“…As the DRAM memory size increases, each refresh operation requires more energy, and more lines need to be refreshed in a given time; therefore, refresh operations become the main source of DRAM power dissipation [31]. To address these issues, the use of emerging nonvolatile memory (NVM) technologies for on-chip memories have attracted much attention [20][21][22][23][24]29]. Many desirable characteristics such as higher density, near zero leakage power, and high resilience against soft errors are some advantages that are offered [25,32].…”