Predictable execution adaptivity through embedding dynamic reconfigurability into static MPSoC schedules

Yang, Chengmo; Orailoğlu, Alex

doi:10.1145/1289816.1289824

Cited by 24 publications

(31 citation statements)

References 18 publications

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“…In this section, we validate the proposed method by comparing the throughput and migration cost with those from the previous work [12], which is called "Band & Band reconfiguration" scheme, BBR shortly, throughout the rest of this paper. For the purpose of comparison, we implemented the scheduling algorithm of the BBR scheme in C++.…”

Section: Methodsmentioning

confidence: 97%

“…The main idea of the BBR scheme is explained with a motivational task graph in Figure 9(a), which is borrowed from [12]. In BBR, scheduling is performed with slight modification of the Critical Path Node Dominate (CPND) algorithm [23].…”

Section: Methodsmentioning

confidence: 99%

“…On the other hand, the technique in [12] is similar to ours in that task-to-processor reconfiguration is determined statically on a processor failure. A set of tasks in a target architecture are statically assigned to one of two bands, which is a geometrical partition of a processor latitude.…”

Section: Related Workmentioning

confidence: 99%

“…However they do not address what to do when failure occurs. On the other hand, works in [12][13] considers processor failures when constructing a static schedule. And they proposed a dynamic task remapping technique at processor failure.…”

Section: Introductionmentioning

confidence: 99%

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A task remapping technique for reliable multi-core embedded systems

Lee

Kim

Park

et al. 2010

Proceedings of the Eighth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis

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With the continuous scaling of semiconductor technology, the life-time of circuit is decreasing so that processor failure becomes an important issue in MPSoC design. A software solution to tolerate run-time processor failure is to migrate tasks from the failed processors to the live processors when failure occurs. Previous works on run-time task migration usually aim to minimize the migration overhead with or without a given latency constraint. For streaming applications, however, it is more important to minimize the throughput degradation than the migration overhead or the latency. Hence, we propose a task remapping technique to minimize the throughput degradation assuming that the migration overhead can be amortized safely. The target multi-core system assumed in this paper consists of processor pools and each pool consists of homogeneous processors. The proposed technique is based on an intensive compile-time analysis for all possible failure scenarios. It involves the following steps; 1) Determine the static mapping of tasks onto the live processors, aiming to minimize the throughput degradation: 2) Find an optimal processor-to-processor mapping to minimize the task migration overhead: and 3) Store the resultant task remapping information that includes task mapping and processor-to-processor mapping results. Since the task remapping information is pre-computed at compile-time for all possible failure scenarios, it should be efficiently represented and stored. At run-time, we simply remap the tasks following the compile-time decision. We examine the scalability of the proposed technique on both space and run-time overhead for compile-time analysis varying the number of failed processors. Through intensive experiments, we show that the proposed technique outperforms the previous works with respect to application throughput.

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Section: Methodsmentioning

confidence: 97%

Section: Methodsmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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A task remapping technique for reliable multi-core embedded systems

Lee

Kim

Park

et al. 2010

Proceedings of the Eighth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis

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“…Other researchers have looked into dynamic configurability according to the dynamic workload. Yang et al [15] tried to use configurability through workload prediction for energy savings. Others investigated application-specific voltage scaling;…”

Section: Related Workmentioning

confidence: 99%

Maximizing Energy Efficiency through Vertically Integrated Dynamic Reconfigurability

Arrabi¹

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Power and energy consumption have become some of the main hurdles for performance advancement in modern digital systems. High transistor densities and clock speeds have created significant thermal and power delivery issues, and increasingly pervasive portable electronic devices have limited energy sources but high performance expectations. Power affects and is affected by almost every aspect of digital system design, enticing designers and researchers to approach this problem from every possible aspect.This work explores two such aspects: dynamic reconfigurability and vertical integration. Dynamic reconfigurability is the ability to change the configuration of the system dynamically during runtime, and vertical integration is using low-level design information in high-level decisions (and vice-versa) as well as co-optimizing multiple design levels simultaneously. Both of these concepts can be targeted to various system metrics; in this work, they are used to reduce the total energy consumption of the system with the goal of increasing system battery lifetime while still providing the necessary performance and functional capabilities.This work explores dynamic reconfigurability and vertical integration through the use of three practical systems. We go through the steps and analysis in designing these systems that will show the potential benefits of our methods. Through the steps of designing the systems, we show the impact of several significant aspects of vertically integrated dynamically configurable systems, thus providing a framework for identifying potential benefits of reconfigurability and co-optimization and for general guidelines of how to implement them on other systems. We also look at the granularity of configurability and the overhead that it incurs, as well as the circuit-level details and information that might affect and be affected by architectural or system-level decisions.The first system is a wireless body sensor node that consumes most of its energy wirelessly transmitting data. We investigate how adaptive software can compress the data before sending without sacrificing information using only the limited processing and memory resources that typically reside on body sensors. We go through the various aspects that affect our solution and the different design levels we have to take into account when applying the compression.The second example system is a custom digital signal-processing system utilizing Panoptic Dynamic Voltage Scaling (PDVS), in which we investigate adding fine-grained spatial and temporal granularities of voltage scaling to the processor. We use a vertically integrated approach to explore the trade-offs of the ability to switch the voltage of a single arithmetic component (spatial) for a single operation (temporal), as well as the different variables that need to be considered for scheduling such systems.The third system is a Field Programmable Core Array (FPCA), in which we investigate various methods for creating a configurable processor capable of switching betwee...

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