Power efficient branch prediction through early identification of branch addresses

Yang, Chengmo; Orailoğlu, Alex

doi:10.1145/1176760.1176782

Cited by 15 publications

(8 citation statements)

References 18 publications

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“…By using a larger buffer size, their BP can make 77,103 Storing history in modulo-N manner 21,54,94 Power-gating based on temporal or spatial locality 48,57,60,104 Avoiding access to BP for biased branches, 68 Reducing BP size by intelligently managing global history [40][41][42][43] Banked-design of BP 68,104 Reducing BP complexity 21 Analog designs 45,46,53 Use of memristor 45,53 FIGURE 37 Pipelined gshare implementation. If a branch was fetched in stage 2, its "new history" bit is shifted from stage 2, and "branch present" bit is set; else, "branch present" bit is reset.…”

Section: Techniques For Reducing Bp Latency and Energymentioning

confidence: 99%

A survey of techniques for dynamic branch prediction

Mittal

2018

Concurrency and Computation

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Branch predictor (BP) is an essential component in modern processors since high BP accuracy can improve performance and reduce energy by decreasing the number of instructions executed on wrong-path. However, reducing the latency and storage overhead of BP while maintaining high accuracy presents significant challenges. In this paper, we present a survey of dynamic branch prediction techniques. We classify the works based on key features to underscore their differences and similarities. We believe this paper will spark further research in this area and will be useful for computer architects, processor designers, and researchers. KEYWORDSdynamic branch predictor, hybrid BP, neural BP, perceptron predictorside BP, pipelining, predictor accuracy, review, side BP, speculative execution, two-level BP INTRODUCTIONControl-changing instructions such as branches add uncertainty in the execution of dependent instructions and thus lead to large performance loss in pipelined processors. To offset their overhead, accurate prediction of branch outcomes is vital. Since branch misprediction incurs high latency (eg, 14 to 25 cycles 1 ) and wastes energy due to execution of instructions on wrong-path, an improvement in BP* accuracy can boost performance and energy efficiency significantly. For example, experiments on real processors showed that reducing the branch mispredictions by half improved the processor performance by 13%. 2Effective design and management of BPs, however, presents several challenges. Design of BP involves a strict tradeoff between area, energy, accuracy, and latency. An increase in BP complexity for improving accuracy may make it infeasible for implementation or offset its performance benefit. For example, a 512 KB perceptron predictor may provide lower instruction-per-cycle than its 32 KB version, 3 and a 2-cycle fully accurate BP may provide lower instruction-per-cycle than a 1-cycle partially inaccurate BP. 4 Further, due to its high access frequency, BP becomes a thermal hot-spot, 5 and hence, reducing its dynamic and leakage energy is important. Clearly, intelligent techniques are required for resolving these issues.Further, recently, researchers have demonstrated two security vulnerabilities viz., "Meltdown" and "Spectre," which exploit speculative execution feature of modern CPUs. 6-8 For example, Spectre vulnerability works on the observation that the speculative execution due to a branch misprediction may leave side effects, which can reveal sensitive data to attackers, eg, if the memory accesses performed during speculative execution depends on sensitive data, the resulting state of the cache forms a side-channel through which the sensitive data can be leaked. These vulnerabilities affect nearly every modern CPU. While avoiding speculative execution (eg, disabling branch prediction) can mitigate these vulnerabilities, it leads to significant performance loss. In light of these vulnerabilities and associated tradeoffs, a deeper study of branch predictors is definitely required. Contributions:In this ...

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Section: Techniques For Reducing Bp Latency and Energymentioning

confidence: 99%

A survey of techniques for dynamic branch prediction

Mittal

2018

Concurrency and Computation

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“…Yang and Orailoglu [34] present a technique to eliminate the wastefulness of accessing the branch predictor every cycle. They do this by statically calculating the length of each basic block in order to know which instructions need branch prediction.…”

Section: Micro-architecturementioning

confidence: 99%

Improving processor efficiency by statically pipelining instructions

et al. 2013

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A new generation of applications requires reduced power consumption without sacrificing performance. Instruction pipelining is commonly used to meet application performance requirements, but some implementation aspects of pipelining are inefficient with respect to energy usage. We propose static pipelining as a new instruction set architecture to enable more efficient instruction flow through the pipeline, which is accomplished by exposing the pipeline structure to the compiler. While this approach simplifies hardware pipeline requirements, significant modifications to the compiler are required. This paper describes the code generation and compiler optimizations we implemented to exploit the features of this architecture. We show that we can achieve performance and code size improvements despite a very low-level instruction representation. We also demonstrate that static pipelining of instructions reduces energy usage by simplifying hardware, avoiding many unnecessary operations, and allowing the compiler to perform optimizations that are not possible on traditional architectures.

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“…We believe that this article's proposals are complementary to both of these techniques and could be advantageous in combination, as the number of accesses are reduced and thus more targets are available for activation of drowsy mode. Yang and Orailoglu [2006] proposed a small branch identification unit and avoided accessing the BTB until the next branch is encountered. However, this approach requires changing executables to store branch distance information and also requires the use of a counter to detect the next branch.…”

Section: Related Workmentioning

confidence: 99%

Reducing instruction fetch energy in multi-issue processors

Gavin

Whalley

Själander

2013

ACM Trans. Archit. Code Optim.

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The need to minimize power while maximizing performance has led to recent developments of powerful superscalar designs targeted at embedded and portable use. Instruction fetch is responsible for a significant fraction of microprocessor power and energy, and is therefore an attractive target for architectural power optimization. We present novel techniques that take advantage of guarantees so that the instruction translation lookaside buffer, branch target buffer, and branch prediction buffer can frequently be disabled, reducing their energy usage, while simultaneously reducing branch predictor contention. These techniques require no changes to the instruction set and can easily be integrated into most single-and multiple-issue processors.

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Power efficient branch prediction through early identification of branch addresses

Abstract: ABSTRACT

Cited by 15 publications

References 18 publications

A survey of techniques for dynamic branch prediction

A survey of techniques for dynamic branch prediction

Improving processor efficiency by statically pipelining instructions

Reducing instruction fetch energy in multi-issue processors

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