Branch Prediction and Power Reduction Techniques in the Clustered Loop Buffer VLIW Architecture

Abstract

The clustered loop buffer VLIW processor has been developed to enhance the performance of multimedia applications in which loop intensive codes are used. In this paper, we employ a dynamic branch predictor in the clustered loop buffer VLIW architecture to handle branch instructions in loop-rich codes, such as multimedia applications, via dynamic speculation. To reduce the energy consumption we map two power reduction techniques, which are hint instruction method and pipeline gating method, on the architecture and analyze their performances using MediaBench applications. In our experiment, we observed that the hint instruction method helps reducing the dynamic branch predictor usage for all the applications tested, by at least 70%. The pipeline gating method was observed to be beneficial to only a subset of the applications with up to 20% of savings.