Low leakage, ultra-thin gate oxides for extremely high performance sub-100 nm nMOSFETs

Abstract

Introduction:We report measurements of the DC characteristics of sub-l00nm nMOSFETs that employ low leakage. ultra-thin gate oxides only 1 -2nm thick to achieve high current drive capability and transconductance. We demonstrate that ZDsctr=: 1.8mAIp.m can be achieved with a 60nm gate at 1.5V using a 1.3-1.4nm gate oxide with a gate leakage current less than 20r~AIp.m~. Furthermore, we find that ZDscrr deteriorates for gate oxides thicker or thinner than this.Fabrication: We have explored a gate stack consisting of l00nm of TEOS hard mask over 80nm of doped W.5, on 1 00nm of in-situ phosphorus-doped poly-crystalline silicon on gate oxides ranging in thickness from 1 -2nm thick on a ptype epitaxial silicon. Prior to the oxide growth, the substrates were stripped by immersion into a 15: 1 H 2 0: HF solution for only 5 seconds (to minimize surface roughness and pitting) and then subjected to a vapor phase clean in 10 Torr

Sub-100 nm /spl Gamma/-gate MOSFETs with self-aligned drain extension formed by solid phase diffusion

“…With 2.7 nm gate oxide, excellent values of mS/mm, mA/µm at V are obtained. These values are comparable to published data of devices with similar dimension [8], [9]. This shows that the excessive drain resistance does not seriously degrade the current drive when the stack length is reasonably small.…”

Observation of oxide breakdown and its effects on the characteristics of ultra-thin-oxide nMOSFET's

“…Possible explanations have been proposed as well. Future generation MOSFET devices will have ultra-thin gate oxides and more significant source/drain-to-gate overlaps [2], [15]. Therefore, it is concluded that reliability will become a more difficult challenge for future MOSFET's.…”

“…T HE aggressive scaling of metal-oxide-semiconductor (MOS) devices has led to the fabrication of highperformance MOSFET's with sub-2-nm gate oxides [1], [2]. However, oxide reliability remains a fundamental challenge [3].…”

Extraction of sheet resistance from four-terminal sheet resistors replicated in monocrystalline films with nonplanar geometries

“…However, it has become evident that the proposed viewing-port configuration may also have significant utility as a means of certifying reference-feature line-widths by highresolution optical-transmission microscopy (HRTEM) methods. Under particular conditions, HRTEM can reveal a lattice- plane count [5], such as that constituting the width of an SOI-MEMS reference feature. The known spacing of silicon lattice planes can thus provide a workable traceability path.…”