Low frequency noise in multi-gate SOI CMOS devices

Zafari, Leily; Jomaah, J.; Ghibaudo, G.

doi:10.1016/j.sse.2007.01.005

Cited by 31 publications

(23 citation statements)

References 12 publications

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“…For these reasons, the study of LF noise in UTTB FDSOI is a key issue for the technology evaluation. Previous works have shown that the LF noise in FDSOI devices should be influenced by the coupling effect between the back and front interfaces [4][5][6][7][8].…”

Section: Introductionmentioning

confidence: 99%

Impact of front-back gate coupling on low frequency noise in 28 nm FDSOI MOSFETs

Theodorou

Ioannidis

Haendler

et al. 2012

2012 Proceedings of the European Solid-State Device Research Conference (ESSDERC)

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Low-frequency (LF) noise has been studied on 28 nm FDSOI devices with ultra-thin silicon film (7 nm) and thin buried oxide (25 nm). A strong dependence of the noise level on the combination of the front and back biasing voltages was observed, and justified by the coupling effect of both Si/High-K dielectric and Si/SiO 2 interface noise sources (channel/front oxide and channel/buried oxide), combined with the change of the Remote Coulomb scattering. From comparisons of the experimental and simulation results, it is shown that the main reason of this dependence is the distance of the charge distribution centroid from the interfaces, which is controlled by both front and back-gate bias voltages, and the way this distance affects the Remote Coulomb scattering coefficient .A new LF noise model approach is proposed to include all these effects. This also allows us to assess the oxide trap density values for both interfaces.

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Section: Introductionmentioning

confidence: 99%

Impact of front-back gate coupling on low frequency noise in 28 nm FDSOI MOSFETs

Theodorou

Ioannidis

Haendler

et al. 2012

2012 Proceedings of the European Solid-State Device Research Conference (ESSDERC)

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“…[The amount of charge at the BOX/silicon layer interface affects the electrical behaviour of SOI CMOS transistors, e.g., threshold voltage and saturation current.] [75,16,26,81] The suppliers of SOI wafers continue to aggressively improve materials quality and reduce cost, driven by the considerable economic motivation of a rapidly growing commercial market for SOI wafers and a clearly defined roadmap for SOI material quality on the ITRS Roadmap [8,105,45,76]. In this fast developing arena, reports of SOI materials quality measurements that are only a year old may be out of date.…”

Section: Soi Challenges and Issuesmentioning

confidence: 99%

“…In this fast developing arena, reports of SOI materials quality measurements that are only a year old may be out of date. Assuming [26,77,80]that the issues of materials quality and cost will be adequately addressed, the adoption of SOI wafers for CMOS fabrication is a non-trivial task. Fabricating CMOS devices in SOI presents challenges in device design and process integration, as well as in the process simulation, device simulation and circuit simulation TCAD tools.…”

Section: Soi Challenges and Issuesmentioning

confidence: 99%

Silicon on Insulator Technology Review

Singh¹,

Saxena²,

Rastogi³

2011

IJESET

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“…However, the initial formulation of the flat band voltage fluctuation was established under approximations which no longer hold true with ultrathin oxide MOSFET devices [6]. Recently several studies have been reported for SOI MOSFETs LFN characterization [3][4][5][6][7][8].…”

Section: A Classical Modelmentioning

confidence: 99%

“…Previous work [8] has considered that activating just one channel in the device, for instance the front channel, would help to characterize just the front oxide defects and remove the coupling effect between the front and back interfaces, but these studies are based on strong assumptions that haven't been numerically verified.…”

Section: A Classical Modelmentioning

confidence: 99%

Low frequency noise modeling of SOI MOSFETs using Green's function approach

ElHusseini¹,

Mart́ınez²,

Armand³

et al. 2011

2011 21st International Conference on Noise and Fluctuations

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In this paper, we present a new numerical model of the inversion charge power spectral density in FDSOI MOSFET devices with ultra thin body. Unlike previous classical models, we don't use the equivalent concept which relates the fluctuation of the oxide charge to the flat-band voltage fluctuation. Localized noise sources in the oxide are implanted into the model and by using a Green's function approach, the spectral cross-correlation of the electrical potential is evaluated at each node in the device mesh in order to obtain a highly accurate physical description. In this paper, we evaluate the validity of the classical model. In view of this, we have compared simulation results to those of the classical formulation and to experimental data. A good agreement with measurements is obtained with the proposed model. The results show that the noise behavior in FDSOI MOSFETs is strongly related to the front and buried oxides defects, even if the channel is located at the front interface. In other words the classical formulation of the flat-band voltage PSD overestimate the front oxide trap density and no more holds true in SOI MOSFETs LFN characterization.

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Low frequency noise in multi-gate SOI CMOS devices

Cited by 31 publications

References 12 publications

Impact of front-back gate coupling on low frequency noise in 28 nm FDSOI MOSFETs

Impact of front-back gate coupling on low frequency noise in 28 nm FDSOI MOSFETs

Silicon on Insulator Technology Review

Low frequency noise modeling of SOI MOSFETs using Green's function approach

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