Low BER performance estimation of LDPC codes via application of importance sampling to trapping sets

Cavus, Enver; Haymes, C.; Daneshrad, Babak

doi:10.1109/tcomm.2009.07.050060

Cited by 46 publications

(33 citation statements)

References 7 publications

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“…Specifically, FPGA simulations in the proximity of the low BER region of interest (e.g., 10 −13 ) are used to obtain the dominant trapping sets (see [9] for more details). Based on these trapping sets, BER is estimated by using importance sampling technique [20]. The excellent accuracy of this method in our application shall be shown in the next section.…”

Section: Performance Evaluation Of Long Ldpc At Very Low Bermentioning

confidence: 98%

Non-Concatenated FEC Codes for Ultra-High Speed Optical Transport Networks

Morero

Castrillon

Ramos³

et al. 2011

2011 IEEE Global Telecommunications Conference - GLOBECOM 2011

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This paper presents a non-concatenated forward error correction (FEC) code suitable for applications in 100Gb/s optical transport networks (OTN). A typical requirement in this application is a net coding gain (NCG) > 10dB at a bit error rate (BER) of 10 −15 with an overhead (OH) of ∼ 20%. As discussed in [1], non-concatenated codes are the ultimate frontier in terms of performance for OTN applications, because of their superior performance, lower latency, and lower overhead than concatenated codes. However, a major stumbling block for the use of these codes has been the existence of BER floors at levels significantly higher than the required 10 −15 (typically 10 −10 ). In this paper we present a new coding scheme based on a low density parity check (LDPC) code with an expected net coding gain of 11.30dB at 10 −15 , 20% OH, and a codeword length of 24576 bits. This represents a significant improvement over the previous state of the art [2], based on a concatenated code with a codeword length of 74844 bits and 20.5% OH. The code is designed to minimize the BER floor while simultaneously reducing the memory requirements and the interconnection complexity of the iterative decoder [3]. Experimental results obtained with an FPGA-based hardware emulator demonstrate an NCG of 10.70dB at a BER of 10 −13 and no error floors. These experimental results are extrapolated to 10 −15 using importance sampling techniques, resulting in the expected performance stated above. Moreover, we find that fixed-point implementation is the main cause of error floors below 10 −13 . Based on this finding, we introduce a new low complexity postprocessing technique to push BER floors down to 10 −15 .

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Section: Performance Evaluation Of Long Ldpc At Very Low Bermentioning

confidence: 98%

Non-Concatenated FEC Codes for Ultra-High Speed Optical Transport Networks

Morero

Castrillon

Ramos³

et al. 2011

2011 IEEE Global Telecommunications Conference - GLOBECOM 2011

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“…While some of the longer codes have lower OH than the prototype code, they have lower density due to their much longer blocklengths. We can therefore expect a lower incidence of intersecting short cycles that cause trapping sets [22], even for the codes with lower OH.…”

Section: B Error Rate Performancementioning

confidence: 97%

“…This gap size was chosen to minimize the appearance of trapping sets in the codes. Trapping set searches on these codes using a heuristic algorithm found nothing, suggesting that these codes have very good error floor performance [22]. Since it is impossible for a regular code with even d v to be full rank, each code was generated with d v = 6 and 1 redundant row, which was then deleted.…”

Section: Code Designmentioning

confidence: 99%

See 1 more Smart Citation

Low-Power 400-Gbps Soft-Decision LDPC FEC for Optical Transport Networks

Cushon

Larsson-Edefors

Andrekson

2016

J. Lightwave Technol.

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We present forward error correction systems based on soft-decision low-density parity check (LDPC) codes for applications in 100-400-Gbps optical transport networks. These systems are based on the low-complexity "adaptive degeneration" decoding algorithm, which we introduce in this paper, along with randomly-structured LDPC codes with block lengths from 30 000 to 60 000 bits and overhead (OH) from 6.7% to 33%. We also construct a 3600-bit prototype LDPC code with 20% overhead, and experimentally show that it has no error floor above a bit error rate (BER) of 10 −15 using a field-programmable gate array (FPGA)-based hardware emulator. The projected net coding gain at a BER of 10 −15 ranges from 9.6 dB at 6.7% OH to 11.2 dB at 33% OH. We also present application-specific integrated circuit synthesis results for these decoders in 28 nm fully depleted silicon on insulator technology, which show that they are capable of 400-Gbps operation with energy consumption of under 3 pJ per information bit. Index Terms-Application-specific integrated circuit (ASIC) synthesis, forward error correction (FEC), low-density parity-check (LDPC) codes, low power.

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“…However, it can not theoretically avoid the underestimate of the error probability because we can not evaluate the whole absorbing sets. The simulation time reduction by the classification of trapping sets [6] can not also give unbiased estimators. Cole et al presented a three-step frame error rate (FER) evaluation method which is constructed by the trapping set search, the error boundary search of the trapping set, and the IS simulation of the FER [7].…”

Section: Introductionmentioning

confidence: 99%

Importance sampling for LDPC codes based on optimal simulation probability density function

Sakai

Shibata

2010

2010 International Symposium on Information Theory &Amp; Its Applications

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This paper shows a fast simulation method of lowdensity parity-check (LDPC) codes by using importance sampling (IS). In IS, the design of the simulation probability density function (PDF) plays a very important role to reduce the simulation time. We derive the optimal simulation PDF, which can reduce the variance of the estimator to zero. Since the optimal simulation PDF includes true error probability, it can not be utilized in the practical simulation. The simulation PDF which approximates the optimal simulation PDF is proposed. In addition, we show some numerical examples to show the effectiveness of the proposed simulation method.

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Low BER performance estimation of LDPC codes via application of importance sampling to trapping sets

Cited by 46 publications

References 7 publications

Non-Concatenated FEC Codes for Ultra-High Speed Optical Transport Networks

Non-Concatenated FEC Codes for Ultra-High Speed Optical Transport Networks

Low-Power 400-Gbps Soft-Decision LDPC FEC for Optical Transport Networks

Importance sampling for LDPC codes based on optimal simulation probability density function

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