This paper presents a non-concatenated forward error correction (FEC) code suitable for applications in 100Gb/s optical transport networks (OTN). A typical requirement in this application is a net coding gain (NCG) > 10dB at a bit error rate (BER) of 10 −15 with an overhead (OH) of ∼ 20%. As discussed in [1], non-concatenated codes are the ultimate frontier in terms of performance for OTN applications, because of their superior performance, lower latency, and lower overhead than concatenated codes. However, a major stumbling block for the use of these codes has been the existence of BER floors at levels significantly higher than the required 10 −15 (typically 10 −10 ). In this paper we present a new coding scheme based on a low density parity check (LDPC) code with an expected net coding gain of 11.30dB at 10 −15 , 20% OH, and a codeword length of 24576 bits. This represents a significant improvement over the previous state of the art [2], based on a concatenated code with a codeword length of 74844 bits and 20.5% OH. The code is designed to minimize the BER floor while simultaneously reducing the memory requirements and the interconnection complexity of the iterative decoder [3]. Experimental results obtained with an FPGA-based hardware emulator demonstrate an NCG of 10.70dB at a BER of 10 −13 and no error floors. These experimental results are extrapolated to 10 −15 using importance sampling techniques, resulting in the expected performance stated above. Moreover, we find that fixed-point implementation is the main cause of error floors below 10 −13 . Based on this finding, we introduce a new low complexity postprocessing technique to push BER floors down to 10 −15 .
A typical high-speed decoder implementation for an LDPC may require hundreds or even thousands of variable and check node processors. Since check node processing unit (CNPU) is far more complex than variable processing unit, hardware requirements of CNPU has a big impact on the final decoder complexity. Here, an FPGA implementation of the soft parity check node for Min-Sum LDPC Decoders is analyzed. The hardware cost and speed of the main block of CNPU, which finds the two smallest input values, is thoroughly studied for different numbers of input values with different bit-widths. Experiments for an FPGA implementation demonstrate that hardware cost and speed vary with the number of input values in the same way as they do for an ASIC implementation. Furthermore, it is shown that more than 60% of the hardware resources of the CNPU is used for finding the two smallest input values.
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