A 90 nm CMOS DSP MLSD Transceiver With Integrated AFE for Electronic Dispersion Compensation of Multimode Optical Fibers at 10 Gb/s

Agazzi, O.E.; Hueda, Mario R.; Crivelli, D.E.; Carrer, H.S.; Nazemi, Ali; Luna, G.; Ramos, Facundo; Lopez, Ramiro; Grace, C.; Kobeissy, B.; Abidin, C.; Kazemi, Mahmoud; Kargar, Mahyar; Márquez, Carlos; Ramprasad, S.; Bollo, F.; Posse, V.; Wang, S.; Asmanis, G.; Eaton, Gareth R.; Swenson, N.; Lindsay, Thomas; Voois, P.

doi:10.1109/jssc.2008.2006232

Cited by 64 publications

(37 citation statements)

References 24 publications

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“…In Figure 2(a) we consider = 0.6 with = 10 and a DFFE with . More precisely, this fact is exploited in the second iteration ( = 1), in which it is observed that the reliability of (1) has been improved as a result of the partial cancellation of the postcursor ISI caused bŷ(…”

Section: Numerical Resultsmentioning

confidence: 99%

“…with (1,0) = (+1, +1), (1,1) = (+1, −1), (1,2) = (−1, +1), and (1,3) = (−1, −1). From (20) and (23), we get…”

Section: Examplementioning

confidence: 99%

“…Future generation of communication systems will operate at multigigabit-per-second data rates on highly dispersive channels [1,2]. In commercial applications, the digital receiver is often implemented as a monolithic chip in CMOS technology [1].…”

Section: Introductionmentioning

confidence: 99%

“…In commercial applications, the digital receiver is often implemented as a monolithic chip in CMOS technology [1]. Maximum clock frequency of state-of-the-art complex digital signal processors in 28 nm CMOS technology is limited to frequencies lower than 1 GHz.…”

Section: Introductionmentioning

confidence: 99%

“…Maximum clock frequency of state-of-the-art complex digital signal processors in 28 nm CMOS technology is limited to frequencies lower than 1 GHz. Therefore, in order to achieve multigigabit-per-second data rates, parallel processing techniques are required [1].…”

Section: Introductionmentioning

confidence: 99%

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A Low-Complexity Decision Feedforward Equalizer Architecture for High-Speed Receivers on Highly Dispersive Channels

Pola

Cousseau

Agazzi³

et al. 2013

Journal of Electrical and Computer Engineering

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This paper presents an improved decision feedforward equalizer (DFFE) for high speed receivers in the presence of highly dispersive channels. This decision-aided equalizer technique has been recently proposed for multigigabit communication receivers, where the use of parallel processing is mandatory. Well-known parallel architectures for the typical decision feedback equalizer (DFE) have a complexity that grows exponentially with the channel memory. Instead, the new DFFE avoids that exponential increase in complexity by using tentative decisions to cancel iteratively the intersymbol interference (ISI). Here, we demostrate that the DFFE not only allows to obtain a similar performance to the typical DFE but it also reduces the compelxity in channels with large memory. Additionally, we propose a theoretical approximation for the error probability in each iteration. In fact, when the number of iteration increases, the error probability in the DFFE tends to approach the DFE. These benefits make the DFFE an excellent choice for the next generation of high-speed receivers.

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Section: Numerical Resultsmentioning

confidence: 99%

“…with (1,0) = (+1, +1), (1,1) = (+1, −1), (1,2) = (−1, +1), and (1,3) = (−1, −1). From (20) and (23), we get…”

Section: Examplementioning

confidence: 99%