In this work, we introduce a unique technique that improves the performance of the BP decoding in waterfall and error-floor regions by reversing the decoder failures. Based on the short cycles existing in the bipartite graph, an importance sampling simulation technique is used to identify the bit and check node combinations that are the dominant sources of error events, called trapping sets. Then, the identified trapping sets are used in the decoding process to avoid the pre-known failures and to converge to the transmitted codeword. With a minimal additional decoding complexity, the proposed technique is able to provide performance improvements for short-length LDPC codes and push or avoid error-floor behaviors of longer codes.
This paper presents a computationally efficient application-specific integrated circuit (ASIC) implementation for the decoding of space-time block codes (STBCs) . Alternative methods of evaluating the originally proposed maximum-likelihood decision metrics are explored at the algorithm and architectural level. At the algorithm level, unique decoding techniques are developed that result in computation savings of as much as 65%. At the architectural level, a low-computation symmetrical approach for the implementation of the proposed algorithm is presented. The proposed ASIC architecture offers considerable computation reductions leading to substantial power and area savings compared to a direct implementation of the original algorithm. The proposed architecture was realized in an ASIC referred to as the ST block decoder ASIC. The chip was fabricated using 0.18-m CMOS technology and occupies a core area of 0.25 mm 2 . The ASIC architecture is highly scalable and can implement 2 2, 8 3, and 8 4 STBCs with modulation formats ranging from binary-phase shift keying (BPSK) to 16 quadrature amplitude modulation (QAM), and can operate at any symbol rate up to 20 Mbaud. Depending on the mode of operation, the decoder power consumption ranges from 0.54 mW for 2 2 BPSK systems to 1.89 mW for 8 4 16-QAM systems.Index Terms-Decoder application-specific integrated circuit (ASIC), low complexity, low power, space-time block codes (STBCs), transmit diversity, 3G.
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