Low-Power 400-Gbps Soft-Decision LDPC FEC for Optical Transport Networks

Abstract

We present forward error correction systems based on soft-decision low-density parity check (LDPC) codes for applications in 100-400-Gbps optical transport networks. These systems are based on the low-complexity "adaptive degeneration" decoding algorithm, which we introduce in this paper, along with randomly-structured LDPC codes with block lengths from 30 000 to 60 000 bits and overhead (OH) from 6.7% to 33%. We also construct a 3600-bit prototype LDPC code with 20% overhead, and experimentally show that it has no error floor above a bit error rate (BER) of 10 −15 using a field-programmable gate array (FPGA)-based hardware emulator. The projected net coding gain at a BER of 10 −15 ranges from 9.6 dB at 6.7% OH to 11.2 dB at 33% OH. We also present application-specific integrated circuit synthesis results for these decoders in 28 nm fully depleted silicon on insulator technology, which show that they are capable of 400-Gbps operation with energy consumption of under 3 pJ per information bit. Index Terms-Application-specific integrated circuit (ASIC) synthesis, forward error correction (FEC), low-density parity-check (LDPC) codes, low power.

Multi-matrix error estimation and reconciliation for quantum key distribution

“…In simulation setups, we first fix N to 3 and construct LDPC codes with four widely used code lengths n = 5000, 10000, 15000, and 25000 [30][31][32][33], each of which includes three code rates R 0 = 0.6, 0.7 and 0.8 for MRCR by the multi-matrix construction method [16] (see Appendix B for details). And for each n and each R 0 , a matrix applied to SRCR is randomly selected from 3 matrices in MRCR.…”

A configurable FPGA FEC unit for Tb/s optical communication

“…First step in decoding of the BCH codes is calculating syndromes (2). Based on the syndromes, the error positions are found by a number of table-look-ups for finding roots in 2 nd and 3 rd degree polynomials.…”

“…in [1], and application of FEC to such high speed links are also reported, [1], [2]. It must be foreseen that several parallel lanes with a lower bit rate could be used, but combined in a single FEC solution.…”

“…Most of the recent research work considers softdecision FEC especially with use of LDPC codes, [2], [6], [7], [8]. In this paper, we focus on hard decision decoding for two reasons: First, soft decisions require a broader interface to the FPGA and this will limit the data rate due to the limited number of transceivers in the FPGA.…”

Binary Message Passing Decoding of Product Codes Based on Generalized Minimum Distance Decoding : (Invited Paper)

“…Several works have attempted to reduce the decoding complexity of BP decoding of LDPC codes, see, e.g., [1]- [4]. For high-throughput applications, an alternative to LDPC codes with (BP) soft decision decoding (SDD) is to consider hard decision decoding (HDD).…”