Leakage-based On-Chip Thermal Sensor for CMOS Technology

Ituero, Pablo; Ayala, José L.; López‐Vallejo, Marisa

doi:10.1109/iscas.2007.378223

Cited by 13 publications

(6 citation statements)

References 13 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In [22], [23], [24] temperature sensors that exploit one or more of transistor characteristics dependent on temperature have been proposed. By measuring temperature as a variable parameter, response mechanisms can be enforced for energy-delay optimization.…”

Section: B Evaluating Yieldmentioning

confidence: 99%

Dynamic fine-grain body biasing of caches with latency and leakage 3T1D-based monitors

Ganapathy

Canal

González

et al. 2011

2011 IEEE 29th International Conference on Computer Design (ICCD)

View full text Add to dashboard Cite

Abstract-In this paper, we propose a dynamically tunable fine-grain body biasing mechanism to reduce active & standby leakage power in caches under process variations. Front body biasing (FBB) is employed for active sub-arrays to speed up accesses while inactive sub-arrays are reverse body biased (RBB) to reduce standby leakage power. Cache subarrays are classified based on run-time leakage and latency distributions and applied bias voltage is updated to account for these changes. This ensures that under all scenarios, the cache will consume the lowest leakage power for the target access latency computed at design-time. The backbone of the hardware used for classification is the 3T1D DRAM cell embedded into conventional 6T based memory. By measuring the access and retention time of the 3T1D cell, we show that it is possible to classify cache arrays based on run-time latency/leakage measurements. The tremendous increase in energy in active mode by forward biasing (to meet latency requirements) is compensated by reverse biasing inactive arrays. Our technique reduces leakage energy consumption and access latency of the cache on average by 20% & 18% respectively when compared to other state-of-the-art proposals. Finally we show that our technique will improve parametric yield by a maximum of 38% for worst-case scenario.

show abstract

Section: B Evaluating Yieldmentioning

confidence: 99%

Dynamic fine-grain body biasing of caches with latency and leakage 3T1D-based monitors

Ganapathy

Canal

González

et al. 2011

2011 IEEE 29th International Conference on Computer Design (ICCD)

View full text Add to dashboard Cite

show abstract

“…These however occupy a large silicon area, have a considerably high power-requirement and are significantly affected by process-variations rendering their usage as sensors unreliable in the sub-90nm regime. Leakage based thermal sensors have been proposed in [21] and [22]. Leakage is a highly processdependent parameter and at higher temperatures the sensorresponse curves become asymptotic making it difficult to discern consecutive measurements and compromising the accuracy of the sensor.…”

Section: Related Workmentioning

confidence: 99%

A 12.4μm<sup>2</sup> 133.4μW 4.56mV/°C resolution digital on-chip thermal sensing circuit in 45nm CMOS utilizing sub-threshold operation

Datta

Burleson

2011

2011 12th International Symposium on Quality Electronic Design

View full text Add to dashboard Cite

Dynamic thermal management (DTM) schemes rely on physical sensors to provide them with feedback to ensure an accurate and closed-loop throttling mechanism. Powerdensity trends in current-generation, high-performance processors motivate the need for multiple low-area, lowpower and high-sensitivity temperature monitoring circuits. To this end, we have proposed and implemented in 45nm CMOS, a novel, digital, on-chip thermal sensing circuit with a high thermal sensitivity of 4.56mV/ºC, low power dissipation of 133.4μW and a compact layout occupying 12.4μ 2 . The design is robust towards process and supply induced noise incurring a 1-σ accuracy loss of <=1.24ºC for a +/-10% random variation in the physical and environmental parameters.

show abstract

“…These however occupy a large silicon area, have a considerably high power-requirement and are significantly affected by processvariations rendering their usage as sensors unreliable in the sub90nm regime. Leakage based thermal sensors have been proposed in [17] and [18]. Leakage is a highly process-dependent parameter and at higher temperatures the sensor-response curves become asymptotic making it difficult to discern consecutive measurements and compromising the accuracy of the sensor.…”

Section: Temperature Monitoring In 3-d 21 Related Workmentioning

confidence: 99%

A high sensitivity and process tolerant digital thermal sensing scheme for 3-D Ics

Datta

Burleson

2011

Proceedings of the 21st Edition of the Great Lakes Symposium on Great Lakes Symposium on VLSI

View full text Add to dashboard Cite

Thermal sensing is a pressing need in stacked 3-D chips with limited number of vertical heat conduits. In 3-D systems with active temperature control, the controller is reliant on sensors placed on individual planes to provide the necessary thermal feedback. To this end we propose a delay-line based thermalsensor which provides a high temperature-sensitivity, high level of process-robustness and is amenable to the TSV-based communication paradigm used in 3D systems. The temperaturesensitive piece mitigates the high process-susceptibility of 3-D circuits through usage of multiple logic-stages composed of longchannel devices and elimination of common-mode noise on the delay-line pair. The thermal information is conveyed to the controller in the form of a signal-frequency and hence is insensitive to path-mismatch in TSV wires. A high postdigitization temperature sensitivity of 0.82%/°C was achieved. The 1-σ accuracy loss due to process-variations and supply-noise was limited to 0.78°C and 1.06°C respectively indicating a high level of process-tolerance.

show abstract

Leakage-based On-Chip Thermal Sensor for CMOS Technology

Cited by 13 publications

References 13 publications

Dynamic fine-grain body biasing of caches with latency and leakage 3T1D-based monitors

Dynamic fine-grain body biasing of caches with latency and leakage 3T1D-based monitors

A 12.4μm<sup>2</sup> 133.4μW 4.56mV/°C resolution digital on-chip thermal sensing circuit in 45nm CMOS utilizing sub-threshold operation

A high sensitivity and process tolerant digital thermal sensing scheme for 3-D Ics

Contact Info

Product

Resources

About

Leakage-based On-Chip Thermal Sensor for CMOS Technology

Cited by 13 publications

References 13 publications

Dynamic fine-grain body biasing of caches with latency and leakage 3T1D-based monitors

Dynamic fine-grain body biasing of caches with latency and leakage 3T1D-based monitors

A 12.4&#x03BC;m<sup>2</sup> 133.4&#x03BC;W 4.56mV/&#x00B0;C resolution digital on-chip thermal sensing circuit in 45nm CMOS utilizing sub-threshold operation

A high sensitivity and process tolerant digital thermal sensing scheme for 3-D Ics

Contact Info

Product

Resources

About

A 12.4μm<sup>2</sup> 133.4μW 4.56mV/°C resolution digital on-chip thermal sensing circuit in 45nm CMOS utilizing sub-threshold operation