LDMOS-transistors on semi-insulating silicon-on-polycrystalline-silicon carbide substrates for improved RF and thermal properties

Lotfi, Sara; Li, Ling-Guang; Vallin, Örjan; Vestling, Lars; Norström, H; Olsson, Jörgen

doi:10.1016/j.sse.2011.11.019

Cited by 17 publications

(17 citation statements)

References 3 publications

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“…Previous studies on Si/SiC electronics have concentrated on demonstrating MOSFET behaviour [13,14] and the implementation of RF devices [15,16]. Both showed that the effects of self-heating on the forward characteristics can be suppressed, unlike equivalent SOI devices power devices.…”

Section: The Si/sic Conceptmentioning

confidence: 99%

“…These studies have shown experimentally [14] that the channel mobility of a Si/SiC MOSFET at 300°C and hence its channel resistance was just 10% worse than it was at room temperature, compared to an 83% reduction for an equivalent Si bulk device. Experimental results from RF devices implemented in a complicated Si/poly-Si/polySiC substrate [16], show that the negative-resistance effect of self-heating (whereby device resistance increases with voltage due to a rise in internal temperature) is minimised in the Si/SiC device, unlike an equivalent SOI device. However, breakdown voltage, [17].…”

Section: The Si/sic Conceptmentioning

confidence: 99%

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Design and Fabrication of Silicon-on-Silicon-Carbide Substrates and Power Devices for Space Applications

et al. 2017

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A new generation of power electronic semiconductor devices are being developed for the benefit of space and terrestrial harsh-environment applications. 200-600 V lateral transistors and diodes are being fabricated in a thin layer of silicon (Si) wafer bonded to silicon carbide (SiC). This novel silicon-on-silicon-carbide (Si/SiC) substrate solution promises to combine the benefits of silicon-on-insulator (SOI) technology (i.e device confinement, radiation tolerance, high and low temperature performance) with that of SiC (i.e. high thermal conductivity, radiation hardness, high temperature performance). Details of a process are given that produces thin films of silicon 1, 2 and 5 μm thick on semi-insulating 4H-SiC. Simulations of the hybrid Si/SiC substrate show that the high thermal conductivity of the SiC offers a junction-to-case temperature ca. 4× less that an equivalent SOI device; reducing the effects of self-heating, and allowing much greater power density. Extensive electrical simulations are used to optimise a 600 V laterally diffused metaloxide-semiconductor field-effect transistor (LDMOSFET) implemented entirely within the silicon thin film, and highlight the differences between Si/SiC and SOI solutions.

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Section: The Si/sic Conceptmentioning

confidence: 99%

Section: The Si/sic Conceptmentioning

confidence: 99%

Design and Fabrication of Silicon-on-Silicon-Carbide Substrates and Power Devices for Space Applications

et al. 2017

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“…However, the SI SiC platform fails to provide a strong 2D RESURF effect for LDMOSFETs, leading to a reduced blocking voltage [3] and an increased electrical resistance [4] when compared with an equivalent SOI. It can be found that there is a trade-off between electrical and thermal resistance in the thin-film Si/ (SI) SiC transistors using 2D RESURF techniques.…”

Section: Introductionmentioning

confidence: 99%

Numerical Study of Energy Capability of Si/SiC LDMOSFETs

Chan

Mawby

et al. 2017

MSF

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Abstract. A comparable study is made on the energy capability of 190 V LDMOSFETs in Si/SiC, SOI, PSOI and PSOSiC technology, using capacitive and inductive switching circuits established in SILVACO Mixed-mode simulators. The results show that the PSOSiC has a thermal advantage compared with other SOI structures under a 48-µs-power-pulse condition, but the Si/SiC device offers superior cooling and energy handling ability in all switching cases despite having a larger chip area.

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“…The Si-on-SiC layer transfer has been performed using SOI bonding techniques, with poly-SiC [16], (SI) 6H-SiC [17] and (SI) 4H-SiC (shown in Fig. 1) [18] being selected as the material of the handle wafers.…”

mentioning

confidence: 99%

“…1) [18] being selected as the material of the handle wafers. The thicknesses of the overlying Si region in [16]- [18] are in the range of 1 to 16 μm, giving wide options to designers aiming at various applications. Shinohara et al [17] have tested the cooling effect offered by 6H-SiC at 300°C, by comparing MOSFETs fabricated in bulk-Si and their 2-in Si/SiC substrates.…”

mentioning

confidence: 99%

Comparative Study of RESURF Si/SiC LDMOSFETs for High-Temperature Applications Using TCAD Modeling

Chan

Sanchez

et al. 2017

IEEE Trans. Electron Devices

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2017) Comparative study of RESURF Si/SiC LDMOSFETs for high-temperature applications using TCAD modeling. IEEE Transactions on Electron Devices, 64 (9). pp. 3713-3718. Permanent WRAP URL:Abstract -This paper analyses the effect of employing an Si on semi-insulating SiC (Si/SiC) device architecture for the implementation of 600-V LDMOSFETs using junction isolation and dielectric isolation reduced surface electric field technologies for high-temperature operations up to 300°C. Simulations are carried out for two Si/SiC transistors designed with either PN or silicon-on-insulator (SOI) and their equivalent structures employing bulk-Si or SOI substrates. Through comparisons, it is shown that the Si/SiC devices have the potential to operate with an offstate leakage current as low as the SOI device. However, the low-side resistance of the SOI LDMOSFET is smaller in value and less sensitive to temperature, outperforming both Si/SiC devices. Conversely, under high-side configurations, the Si/SiC transistors have resistances lower than that of the SOI at high substrate bias, and invariable with substrate potential up to −200 V, which behaves similar to the bulk-Si LDMOS at 300 K. Furthermore, the thermal advantage of the Si/SiC over other structures is demonstrated by using a rectangle power pulse setup in Technology Computer-Aided Design simulations.Index Terms-High-temperature operation, Power LDMOSFETs, reduced surface electric field (RESURF), semiconductor device modeling, silicon carbide, siliconon-insulator technology, silicon-on-silicon carbide.

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LDMOS-transistors on semi-insulating silicon-on-polycrystalline-silicon carbide substrates for improved RF and thermal properties

Cited by 17 publications

References 3 publications

Design and Fabrication of Silicon-on-Silicon-Carbide Substrates and Power Devices for Space Applications

Design and Fabrication of Silicon-on-Silicon-Carbide Substrates and Power Devices for Space Applications

Numerical Study of Energy Capability of Si/SiC LDMOSFETs

Comparative Study of RESURF Si/SiC LDMOSFETs for High-Temperature Applications Using TCAD Modeling

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