JFET/SOS devices. I. Transistor characteristics and modeling results

Halle, L. F.; Knudsen, J.F.

doi:10.1109/16.2461

Cited by 6 publications

(8 citation statements)

References 14 publications

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“…Equation (2) is given in a closed form relation using a = 4.0. as resulted from the optimization program [1] for a particular process structure [3]. Thus Equations (2) and (3) are also valid in the saturation region, beyond channel pinch off.…”

Section: Soi Jfet Analytical Model and Simulationmentioning

confidence: 98%

“…Verification of the optimization program is given in Fig. 3 where a comparison of the mobility-versus-y as obtained from the program and from measurements [3] is presented.…”

Section: Soi Jfet Analytical Model and Simulationmentioning

confidence: 99%

“…1. The channel depth (a) is =0.054 -0.148 pm for enhancement type JFETs and =0.185 -0.265 ~m in case of depletion type JFETs [3].…”

Section: Process-dependent Mobility Modelmentioning

confidence: 99%

“…It also represents much improvement (500%) as compared to device-level simulation using PISCES-II. The doping profiles used in PISCES-II were simulated from the process simulator SUPREME-II [3], where these device and process simulation programs do not account for the influence of the silicon/insulator interface on the electron mobility. The simulated results using the accurate process-dependent circuit-model are within 3% from experimental measurements, shown in Figs.…”

Section: Soi Jfet Analytical Model and Simulationmentioning

confidence: 99%

“…A special case of the model for SiliconOn-Sapphire (SOS) JFTs was introduced by the authors in [1,2]. The interface between Si and Sapphire has two main effects on the device performance [3,4,5]: The first is due to lattice mismatch between the Si layer and the substrate, which causes high density of defects, such as stacking faults, misfit and other dislocations. The second is due to thermal mismatch, as the thermal expansion of sapphire is ~ 2 times the thermal expansion of Si.…”

Section: Introductionmentioning

confidence: 99%

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Process-Dependent Circuit Modeling and Simulation of SOI JFETs: Digital VLSI Applications

Abdel-Aty-Zohdy

Talkhan

1993

SIMULATION

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Accurate circuit modeling and simulation ofSilicon-on-Insulator (SOI) enhancement and depletion Junction Field-Effect transistors (JFETs) is presented. The nonuniformity in FET device parameters along the channel depth (due to fabrication processes), is taken into account. This is typical in SOI and other thin-film structures. Since SOI fabrication processes parameters are represented, in our model, by a closed form mobility variation, improved model accuracy is guaranteed. Simulation results are found to be within less than 3% of actual measurements. Small-signal circuit-model parameters are determined for SOI FJETs and then evaluated for further logic applications. Inverters with a channel Enhancenient-JFET (E-JFET) drivers and nchannel depletion-JFET loads (E/D inverters) are also considered with different supply voltage values, device parameters and digital applications.

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Section: Soi Jfet Analytical Model and Simulationmentioning

confidence: 98%

“…Verification of the optimization program is given in Fig. 3 where a comparison of the mobility-versus-y as obtained from the program and from measurements [3] is presented.…”

Section: Soi Jfet Analytical Model and Simulationmentioning

confidence: 99%

“…1. The channel depth (a) is =0.054 -0.148 pm for enhancement type JFETs and =0.185 -0.265 ~m in case of depletion type JFETs [3].…”

Section: Process-dependent Mobility Modelmentioning

confidence: 99%

Section: Soi Jfet Analytical Model and Simulationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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