Evaluation of silicon-on-sapphire enhancement JFETs for digital applications

Talkhan, Ihab; Abdel-Aty-Zohdy, H.S.

doi:10.1109/glsv.1991.143991

Cited by 1 publication

(1 citation statement)

References 3 publications

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“…This compares tõ u == 6.75~ andtpd=0.4ns in case of a similar parameters nMOS inverter. In [16] a brief comparison between CMOS, nMOS and SOS n-channel JFET inverters is given. The comparison is summarized in Table 1.…”

Section: E-jfet Invertersmentioning

confidence: 99%

Process-Dependent Circuit Modeling and Simulation of SOI JFETs: Digital VLSI Applications

Abdel-Aty-Zohdy

Talkhan

1993

SIMULATION

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Accurate circuit modeling and simulation ofSilicon-on-Insulator (SOI) enhancement and depletion Junction Field-Effect transistors (JFETs) is presented. The nonuniformity in FET device parameters along the channel depth (due to fabrication processes), is taken into account. This is typical in SOI and other thin-film structures. Since SOI fabrication processes parameters are represented, in our model, by a closed form mobility variation, improved model accuracy is guaranteed. Simulation results are found to be within less than 3% of actual measurements. Small-signal circuit-model parameters are determined for SOI FJETs and then evaluated for further logic applications. Inverters with a channel Enhancenient-JFET (E-JFET) drivers and nchannel depletion-JFET loads (E/D inverters) are also considered with different supply voltage values, device parameters and digital applications.

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Section: E-jfet Invertersmentioning

confidence: 99%