Ion beam testing of ALTERA APEX FPGAs

Ceschia, M.; Bellato, M.; Paccagnella, A.; Kaminski, A.

doi:10.1109/redw.2002.1045531

Cited by 40 publications

(21 citation statements)

References 2 publications

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“…Previous work on soft error rate estimation is mainly simulation-based, radiation-based, or a combination of both [1], [2], [7]- [9], [11]- [13], [19], [23], [32]. Most of these methods have been based on Fault Injection (FI) strategies.…”

Section: Previous Workmentioning

confidence: 99%

“…There is a plethora of radiation-based methods which use accelerated radiation testing to measure the sensitivity of FPGA devices to SEUs [7]- [9], [11], [19], [36]. In these approaches, a prototype of the system under study is exposed to a flux of radiation, originated either by radioactive sources or by particle accelerators.…”

Section: Previous Workmentioning

confidence: 99%

“…After computing system failure probabilities for any particular clock cycle after the SEU event, the failure probability for this period (i.e., from the clock cycle at which the bit-flip occurs to clock cycles after that) is computed as follows: (9) After computing for all nodes, the system failure rate can be computed as follows: (10) Note that the complexity of the simulation-based FI method increases exponentially with , making simulation-based analysis intractable for large sequential circuits. However, our approach requires only a matrix multiplication to compute the system failure rate in the subsequent clock cycles, and hence, its time complexity is linear with .…”

Section: Theoremmentioning

confidence: 99%

“…Therefore, it is expected that the term element of to become (or tend to) zero for very large . This means that (9) saturates for large . In our case study, we have noted that this equation saturates for values of 60 to 100 clock cycles.…”

Section: E Accuracy Of the Proposed Theoremmentioning

confidence: 99%

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Soft Error Susceptibility Analysis of SRAM-Based FPGAs in High-Performance Information Systems

Asadi¹,

Tahoori

Mullins³

et al. 2007

IEEE Trans. Nucl. Sci.

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Abstract-Soft errors due to cosmic particles are a growing reliability threat for VLSI systems. The vulnerability of FPGA-based designs to soft errors is higher than ASIC implementations since the majority of chip real estate is dedicated to memory bits, configuration bits, and user bits. Moreover, single event upsets (SEUs) in the configuration bits of SRAM-based FPGAs result in permanent errors in the mapped design.In this paper we analyze the soft error vulnerability of FPGAs used in information systems. Since the reliability requirements of these high performance information subsystems are very stringent, the reliability of the FPGA chips used in the design of such systems plays a critical role in overall system reliability. We present an analytical approach (versus fault injection) for soft error rate estimation in FPGA-based designs. We also validate the projections produced by our analytical model using field error rates obtained from failure data obtained from a large FPGA-based design used in the Logical Unit Module board of a commercial information system. This comparison confirms that the projections obtained from our analytical tool are accurate (there is an 81% overlap in FIT rate range obtained with our analytical modeling framework and the field failure data studied).Index Terms-Error analysis, field programmable gate arrays (FPGA), information systems, logic circuit fault tolerance, reliability estimation, reliability modeling, SRAM chips (SRAM-based FPGAs).

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Section: Previous Workmentioning

confidence: 99%

Section: Previous Workmentioning

confidence: 99%

Section: Theoremmentioning

confidence: 99%

Section: E Accuracy Of the Proposed Theoremmentioning

confidence: 99%

See 2 more Smart Citations

Soft Error Susceptibility Analysis of SRAM-Based FPGAs in High-Performance Information Systems

Asadi¹,

Tahoori

Mullins³

et al. 2007

IEEE Trans. Nucl. Sci.

View full text Add to dashboard Cite

show abstract

“…operations of FPGAs [3][4] causing unexpected output results, usually called Single Event Functional Interrupts (SEFIs). It is becoming of primary concern the possibility of forecasting the effects of SEUs into the configuration memory of a SRAM-based FPGA, possibly starting already in the initial design, when only a highlevel model of the system is available and to possibly intervene in order to guarantee the desired degree of dependability.…”

Section: Introductionmentioning

confidence: 99%