Soft Error Susceptibility Analysis of SRAM-Based FPGAs in High-Performance Information Systems

Asadi, Hossein; Tahoori, Mehdi B.; Mullins, Brian; Kaeli, David; Granlund, Kevin

doi:10.1109/tns.2007.910426

Cited by 65 publications

(17 citation statements)

References 36 publications

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“…The detection and localization of error is implemented as a partial reconfigurable module which is itself subject to errors. A Previous approach based on fine-granularity error masking have been developed in [16], such solution however is only applied to TMR technique on majority voter logic scheme. Vice versa, a first overview of recovery architectures for high computational system based on SRAM-based FPGAs have been presented in [17] and [18].…”

Section: Related Workmentioning

confidence: 99%

An error-detection and self-repairing method for dynamically and partially reconfigurable systems

Reorda

Sterpone

Ullah

2013

2013 18th Ieee European Test Symposium (Ets)

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Reconfigurable systems are gaining an increasing interest in the domain of safety-critical applications, for example in space and avionic applications. In fact, the capability of reconfiguring the system during run-time execution and the high computational power of modern Field Programmable Gate Arrays (FPGAs) makes these devices suitable for data processing. Moreover, such systems must also guarantee the abilities of selfawareness, self-diagnosis and self-repair in order to cope with errors due to the harsh conditions typically existing in some environments. In this paper we propose a self-repairing method for partially and dynamically reconfigurable systems applied at a fine-grain granularity level. Our method is able to recover and correct errors using the run-time partial reconfiguration capabilities offered by modern SRAM-based FPGAs. Fault injection experiments have been executed on a dynamically reconfigurable system embedding a number of benchmark circuits. Results demonstrate that the method can achieve full detection of single and multiple errors, while significantly improving the system availability with respect to traditional error detection and correction methods.

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Section: Related Workmentioning

confidence: 99%

An error-detection and self-repairing method for dynamically and partially reconfigurable systems

Reorda

Sterpone

Ullah

2013

2013 18th Ieee European Test Symposium (Ets)

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“…Previous work estimating SEU-induced failure rate in SRAM-based FPGAs is mainly hardware emulation-based, radiation-based, or a combination of both [Rebaudengo et al 2002;Johnson et al 2003;Graham et al 2003;Bellato et al 2004;Heron et al 2005;Asadi et al 2007]. They use the fault injection strategy and perform hardware emulation on fabricated devices to collect probabilities that the faults can be sensitized by primary inputs and propagated to primary outputs.…”

Section: Failure Rate Estimationmentioning

confidence: 99%

SEU fault evaluation and characteristics for SRAM-based FPGA architectures and synthesis algorithms

Jing

Lee

Feng

et al. 2013

ACM Trans. Des. Autom. Electron. Syst.

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Reliability has become an increasingly important concern for SRAM-based field programmable gate arrays (FPGAs). Targeting SEU (single event upset) in SRAM-based FPGAs, this article first develops an SEU evaluation framework that can quantify the failure sensitivity for each configuration bit during design time. This framework considers detailed fault behavior and logic masking on a post-layout FPGA application and performs logic simulation on various circuit elements for fault evaluation. Applying this framework on MCNC benchmark circuits, we first characterize SEUs with respect to different FPGA circuits and architectures, for example, bidirectional routing and unidirectional routing. We show that in both routing architectures, interconnects not only contribute to the lion's share of the SEU-induced functional failures, but also present higher failure rates per configuration bits than LUTs. Particularly, local interconnect multiplexers in logic blocks have the highest failure rate per configuration bit. Then, we evaluate three recently proposed SEU mitigation algorithms, IPD, IPF, and IPV, which are all logic resynthesis-based with little or no overhead on placement and routing. Different fault mitigating capabilities at the chip level are revealed, and it demonstrates that algorithms with explicit consideration for interconnect significantly mitigate the SEU at the chip level, for example, IPV achieves 61% failure rate reduction on average against IPF with about 15%. In addition, the combination of the three algorithms delivers over 70% failure rate reduction on average at the chip level. The experiments also reveal that in order to improve fault tolerance at the chip level, it is necessary for future fault mitigation algorithms to concern not only LUT or interconnect faults, but also their interactions. We envision that our framework can be used to cast more useful insights for more robust FPGA circuits, architectures, and better synthesis algorithms.

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“…routing switches) [5]. Type 1 is transient because the faulty bit can be overwritten, while type 2 is permanent because the configuration bits remain unchanged until configuration bit stream re-downloaded into the FPGA [6].…”

Section: Introductionmentioning

confidence: 99%

Co-evolutionary Approach to Reduce Soft Error Rate of Implemented Circuits on SRAM_based FPGA

Jahanirad¹

2018

IJCA

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Soft errors such as Single Event Upset (SEU) have great effect on performance degradation of circuits implemented on SRAM_based FPGA. The soft error in configuration bits which control the logic and routing parts of the circuit, leads to permanent faults. In this paper, we have developed a coevolutionary method to reduce the effect of soft error on the implemented circuit on FPGA. This method is based on cooperation of genetic algorithm and ant colony optimization. The efficiency of co-evolutionary method has been proved by comparison of its results with the proposed genetic algorithm and ant colony optimization. The experimental results for some MCNC benchmark circuits show up to 34% improvement compare to genetic algorithm and up to 60% improvement against ant colony optimization.

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Soft Error Susceptibility Analysis of SRAM-Based FPGAs in High-Performance Information Systems

Cited by 65 publications

References 36 publications

An error-detection and self-repairing method for dynamically and partially reconfigurable systems

An error-detection and self-repairing method for dynamically and partially reconfigurable systems

SEU fault evaluation and characteristics for SRAM-based FPGA architectures and synthesis algorithms

Co-evolutionary Approach to Reduce Soft Error Rate of Implemented Circuits on SRAM_based FPGA

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