Investigation of Single-Event Damages on Silicon Carbide (SiC) Power MOSFETs

Mizuta, Eiichi; Kuboyama, S.; Abe, Hiroshi; Iwata, Y.; Tamura, Takashi

doi:10.1109/tns.2014.2336911

Cited by 111 publications

(64 citation statements)

References 12 publications

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“…Heavy ion data for SiC MOSFETs from Wolfspeed, the C2M0080120D (1200 V, 80 m ), showing SEB threshold as a function of deposited energy in the 10-μm-thick lightly doped epi region are given in Fig. 2 [14], [18], [19]. The second scale on the x-axis in Fig.…”

Section: Heavy Ion Datamentioning

confidence: 99%

“…3-D TCAD heavy-ion simulations were used to map out the most sensitive ion entry points in the device (normal incidence was assumed) [14] to develop a sensitive area. The 3-D TCAD simulation results for the most sensitive strike location are compared to heavy ion data [14], [18], [19] in Fig. 2, and the simulated heavy ions have a range consistent with the heavy ions in the beam, which is significantly longer than the thickness of the epi region.…”

Section: Long-range Ion-induced Seb Sensitive Volumementioning

confidence: 99%

“…Even more challenging is modeling neutron SEB, which requires the definition of the sensitive volume (SV) in the [14], [18], [19] and 3-D TCAD simulation results. The second x-axis represents the LET corresponding to each value of deposited energy in the epi region.…”

Section: Introductionmentioning

confidence: 99%

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Estimating Terrestrial Neutron-Induced SEB Cross Sections and FIT Rates for High-Voltage SiC Power MOSFETs

Ball

Sierawski

Galloway

et al. 2019

IEEE Trans. Nucl. Sci.

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Cross sections and failure in time rates for neutroninduced single-event burnout (SEB) are estimated for SiC power MOSFETs using a method based on combining results from heavy ion SEB experimental data, 3-D TCAD prediction of sensitive volumes, and Monte Carlo radiation transport simulations of secondary particle production. The results agree well with experimental data and are useful in understanding the mechanisms for neutron-induced SEB data. Index Terms-Cross section, failure in time (FIT), heavy ion, Monte Carlo, MOSFET, Monte Carlo radiative energy deposition (MRED), neutron, power, silicon carbide (SiC), singleevent burnout (SEB).

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Section: Heavy Ion Datamentioning

confidence: 99%

Section: Long-range Ion-induced Seb Sensitive Volumementioning

confidence: 99%

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Estimating Terrestrial Neutron-Induced SEB Cross Sections and FIT Rates for High-Voltage SiC Power MOSFETs

Ball

Sierawski

Galloway

et al. 2019

IEEE Trans. Nucl. Sci.

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“…However, SiC power diodes and metal oxide semiconductor field-effect transistors (MOSFETs) have been shown to be susceptible to both heavy-ion leakage current degradation (defined as increases in leakage current owing to ion strikes), with damage occurring at biases as low as 20% of M anuscript submitted July 5 th their rated breakdown voltage [2], [3]. This degradation has been characterized as two voltage controlled current sources in series which are together in parallel with a pristine Schottky structure [4].…”

mentioning

confidence: 99%

Unifying Concepts for Ion-Induced Leakage Current Degradation in Silicon Carbide Schottky Power Diodes

Johnson

Javanainen

Raman

et al. 2020

IEEE Trans. Nucl. Sci.

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Reed, R. A.; Schrimpf, R. D.; Alles, J. M.; Lauenstein, J. M.; Javanainen, A.; Raman, A.; Chakraborty, P. S. et al. (2020). Unifying Concepts for Ion-Induced LeakageAbstract-The onset of ion-induced reverse leakage current in SiC Schottky diodes is shown to depend on material properties, ion LET, and bias during irradiation, but not the voltage rating of the parts. This is demonstrated experimentally for devices from multiple manufacturers with voltage ratings from 600 V to 1700 V. Using a device with a higher breakdown voltage than required in the application does not provide increased robustness related to leakage current degradation, compared to using a device with a lower voltage rating.

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“…Silicon carbide (SiC) devices have high breakdown fields and thermal conductivities compared with silicon-based devices and are highly attractive for high-power applications in both aerospace and on the ground, but they are also more sensitive to energetic particles [115][116][117]. In the past ten years, scientists in Finland and other countries have studied the influence of high-energy particles on SiC devices.…”

Section: Influence Of High-energy Particles On Semiconductor Devicesmentioning

confidence: 99%

TSV Technology and High-Energy Heavy Ions Radiation Impact Review

Tian

Liu

2018

Electronics

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Three-dimensional integrated circuits (3D IC) based on TSV (Through Silicon Via) technology is the latest packaging technology with the smallest size and quality. As a result, it can effectively reduce parasitic effects, improve work efficiency, reduce the power consumption of the chip, and so on. TSV-based silicon interposers have been applied in the ground environment. In order to meet the miniaturization, high performance and low-cost requirements of aerospace equipment, the adapter substrate is a better choice. However, the transfer substrate, as an important part of 3D integrated circuits, may accumulate charge due to heavy ion irradiation and further reduce the performance of the entire chip package in harsh space radiation environment or cause it to fail completely. Little research has been carried out until now. This article summarizes the research methods and conclusions of the research on silicon interposers and TSV technology in recent years, as well as the influence of high-energy heavy ions on semiconductor devices. Based on this, a series of research methods to study the effect of high-energy heavy ions on TSV and silicon adapter plates is proposed.Electronics 2018, 7, 112 2 of 29 wafer was invented by M.G Smith et al. [2], which opposite surfaces were connected ohmically to the degenerately doped portions to be electrically connected along the thru-connection. With further research and exploration, 2.5D/3D integration technology with TSV realized integrated circuits with advantages of high interconnection density, high performance, low power consumption, and low cost [3,4]. In addition, the core is widely considered to be the leading technology in the field of high density packaging in the future and is an effective way to break through Moore's Law [5][6][7]. Figure 1. Silicon interposer through electrical copper coating technology production: (a) The construction of through-silicon via on the wafer; (b) The dry film etchant is stuck on the wafer, then exposed and etched; (c) Hole plating and pad fabrication by electroplating methods; (d) The photoresist removing. Adapted with permission from [27], Copyright Elsevier, 2016.

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Investigation of Single-Event Damages on Silicon Carbide (SiC) Power MOSFETs

Cited by 111 publications

References 12 publications

Estimating Terrestrial Neutron-Induced SEB Cross Sections and FIT Rates for High-Voltage SiC Power MOSFETs

Estimating Terrestrial Neutron-Induced SEB Cross Sections and FIT Rates for High-Voltage SiC Power MOSFETs

Unifying Concepts for Ion-Induced Leakage Current Degradation in Silicon Carbide Schottky Power Diodes

TSV Technology and High-Energy Heavy Ions Radiation Impact Review

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