The present work considers electrothermal simulation of LDMOS devices and associated nonequilibrium effects. Simulations have been performed on three kinds of LDMOS: bulk Si, partial SOI and full SOI. Differences between equilibrium and nonequilibrium modeling approaches are examined. The extent and significance of thermal nonequilibrium is determined from phonon temperature distributions obtained using a common electronic solution and three different heating models (Joule heating, electron/lattice scattering, phonon scattering). The results indicate that, under similar operating conditions, nonequilibrium behavior is more significant in the case of full SOI devices, where the extent of nonequilibrium is estimated to be twice that of the partial SOI device and four times that of the bulk device. Time development of acoustic phonon and lattice temperatures in the electrically active region indicates that nonequilibrium effects are significant for times less than 10 ns.
Ion-induced degradation and catastrophic failures in high-voltage SiC Junction Barrier Schottky (JBS) power diodes are investigated. Experimental results agree with earlier data showing discrete jumps in leakage current for individual ions, and show that the boundary between leakage current degradation and a single-event-burnout-like effect is a strong function of LET and reverse bias. TCAD simulations show high localized electric fields under the Schottky junction, and high temperatures generated directly under the Schottky contact, consistent with the hypothesis that the ion energy causes eutectic-like intermixture at the metal-semiconductor interface or localized melting of the silicon carbide lattice.Index Terms-Single event effects, heavy ions, silicon carbide, power diodes, junction barrier schottky (JBS) diode, single-event burnout, thermal coefficients of silicon carbide.
Three-dimensional (3D) stacked integrated circuits (ICs) can significantly improve circuit performance and offer the promise of integrating various technologies (memory, logic, RF, mixed-signal, optoelectronics) within a single block. Lack of 3D design tools and heat dissipation from vertically stacked multiple layers are the crucial problems in their development. To address these issues, CFD Research Corporation (CFDRC) is developing methodologies and tools to analyze and assess coupled electrical and thermal performance of 3D ICs, including calculation of realistic full-chip thermal distributions and determining from them signal delay/distortion. Due to the stacking technology, extensive localized heating can occur. Analysis to minimize these hot spots using thermal vias is demonstrated. Our Python-script based framework allows to drive and control all the aspects of the 3D model building (directly from layouts), thermal simulations, and results extractiodpost-processing. Hence, it is a good basis for coupling with Electronic Design Automation (EDA) systems. We present results of automated, fast, but detailed thermal simulations of 3D stacked integrated circuits. In addition, procedures for automatic extraction of reduced and compact thermal-resistance-based 3D models have been implemented. These techniques greatly reduce required computational time, and allow for very fast parametric modeling analysis of 3D IC design configurations and temperature extraction. From these thermal resistance models, equivalent SPICE netlists may be generated and used for independent or coupled thermal analysis.
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