Introspective 3D chips

Mysore, Shashidhar; Agrawal, Banit; Srivastava, Navin; Lin, Sung-Chyr; Banerjee, Kaustav; Sherwood, Timothy

doi:10.1145/1168857.1168890

Cited by 37 publications

(19 citation statements)

References 38 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…c 2017 Information Processing Society of Japan ies and whitepapers on 3D integration indicate the potential for trustworthy 3D chips as well [139], [140].…”

Section: Towards Trustworthy 3d Integrationmentioning

confidence: 99%

Large-Scale 3D Chips: Challenges and Solutions for Design Automation, Testing, and Trustworthy Integration

Knechtel

Sinanoglu

Elfadel

et al. 2017

IPSJ Transactions on System LSI Design Methodology

View full text Add to dashboard Cite

Three-dimensional (3D) integration of electronic chips has been advocated by both industry and academia for many years. It is acknowledged as one of the most promising approaches to meet ever-increasing demands on performance, functionality, and power consumption. Furthermore, 3D integration has been shown to be most effective and efficient once large-scale integration is targeted for. However, a multitude of challenges has thus far obstructed the mainstream transition from "classical 2D chips" to such large-scale 3D chips. In this paper, we survey all popular 3D integration options available and advocate that using an interposer as system-level integration backbone would be the most practical for large-scale industrial applications and design reuse. We review major design (automation) challenges and related promising solutions for interposer-based 3D chips in particular, among the other 3D options. Thereby we outline (i) the need for a unified workflow, especially once full-custom design is considered, (ii) the current design-automation solutions and future prospects for both classical (digital) and advanced (heterogeneous) interposer stacks, (iii) the state-of-art and open challenges for testing of 3D chips, and (iv) the challenges of securing hardware in general and the prospects for large-scale and trustworthy 3D chips in particular.

show abstract

“…c 2017 Information Processing Society of Japan ies and whitepapers on 3D integration indicate the potential for trustworthy 3D chips as well [139], [140].…”

Section: Towards Trustworthy 3d Integrationmentioning

confidence: 99%

Large-Scale 3D Chips: Challenges and Solutions for Design Automation, Testing, and Trustworthy Integration

Knechtel

Sinanoglu

Elfadel

et al. 2017

IPSJ Transactions on System LSI Design Methodology

View full text Add to dashboard Cite

show abstract

“…The work in this paper is most closely related to the work by Mysore et al [24]. That work focuses on implementing software profiling and analysis engines on the second die.…”

Section: Related Workmentioning

confidence: 99%

“…For customers that require high reliability, the lower die is combined with a corresponding upper die that incorporates a checker core to monitor the register values produced on the inter-die pillars (shown in Figure 2(c)). This "snap-on" functionality of 3D dies was recently proposed by Mysore et al [24] to implement software profiling and debugging tools. This paper proposes a snap-on 3D checker core and various aspects of such an organization are discussed next.…”

Section: Proposed 3d Implementationmentioning

confidence: 99%

See 1 more Smart Citation

Leveraging 3D Technology for Improved Reliability

Madan¹,

Balasubramonian²

2007

40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2007)

View full text Add to dashboard Cite

show abstract

“…General Purpose: Generalizing from these on-chip program profiling and analysis systems, several prior works have proposed methods to dynamically insert instructions into the execution stream [6] to alternate cores in CMPs [23], [32] to specialized profiling co-processors [41], reconfigurable monitors [28] and 3D introspection engines [15]. FlexiTaint [35] and Raksha [9] generalize uniprocessor hardware support for information flow tracking (Note that Raksha prototypes full systems on FPGAs, while we use FPGAs as coprocessors for existing systems).…”

Section: Related Workmentioning

confidence: 99%

Quantifying the Potential of Program Analysis Peripherals

Tiwari

Mysore

Sherwood

2009

2009 18th International Conference on Parallel Architectures and Compilation Techniques

Self Cite

View full text Add to dashboard Cite

Abstract-As programmers are asked to manage more complicated parallel machines, it is likely that they will become increasingly dependent on tools such as multi-threaded data race detectors, memory bounds checkers, dynamic dataflow trackers, and various performance profilers to understand and maintain their software. As these tools continue to grow in importance, it is worth exploring the potential for special purpose accelerators for these tasks, especially since commodity multi-cores can only provide limited speedups. Rather than performing all the instrumentation and analysis on the main processor, we explore the idea of using the increasingly highthroughput board level interconnect available on many systems to offload analysis to a parallel off-chip accelerator. There are many non-trivial technical issues in taking such an approach that may not appear in simulation, and to flush them out we have developed a prototype system that maps a DMA based analysis engine, sitting on a PCI-mounted FPGA, into the Valgrind instrumentation framework. Using this prototype we characterize the potential of such a system to both accelerate existing software development tools and enable a new class of heavyweight dynamic analysis. While many issues still remain with such an approach, we demonstrate that program analysis speedups of 29% to 440% could be achieved today with strictly off-the-shelf components on some of the state-of-the-art tools, and we carefully quantify the bottlenecks to illuminate several new opportunities for further architectural innovation.

show abstract

Introspective 3D chips

Cited by 37 publications

References 38 publications

Large-Scale 3D Chips: Challenges and Solutions for Design Automation, Testing, and Trustworthy Integration

Large-Scale 3D Chips: Challenges and Solutions for Design Automation, Testing, and Trustworthy Integration

Leveraging 3D Technology for Improved Reliability

Quantifying the Potential of Program Analysis Peripherals

Contact Info

Product

Resources

About