Leveraging 3D Technology for Improved Reliability

Madan, Niti; Balasubramonian, Rajeev

doi:10.1109/micro.2007.4408258

Cited by 8 publications

(11 citation statements)

References 32 publications

(59 reference statements)

Supporting

Mentioning

Contrasting

Order By: Relevance

“…It has been also demonstrated that a 3D design can be utilized to improve reliability [11]. However, the adoption of a 3D integration technology faces the challenges of increasing chip temperature due to increasing power density compared to a planar 2D design.…”

Section: D Integration Techniquesmentioning

confidence: 99%

“…The Network-on-Chip (NoC) architecture paradigm, based on a modular packet-switched mechanism, can address many of the on-chip communication design issues, and thus, has been a major research thrust spanning across several design coordinates. These include high performance [1][2][3][4], energy-efficient [5][6][7], fault-tolerant [8][9][10], and areaefficient designs [7,11,12]. While all these studies, except a few [4,7,11,12], are targeted for 2D architectures, we believe that the emerging 3D technology provides ample opportunities to examine the NoC design space.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

MIRA: A Multi-layered On-Chip Interconnect Router Architecture

Park

Eachempati

Das

et al. 2008

2008 International Symposium on Computer Architecture

View full text Add to dashboard Cite

Recently, Network-on-Chip (NoC) architectures have gained popularity to address the interconnect delay problem for designing CMP / multi-core / SoC systems in deep sub-micron technology. However, almost all prior studies have focused on 2D NoC designs. Since three dimensional (3D) integration has emerged to mitigate the interconnect delay problem, exploring the NoC design space in 3D can provide ample opportunities to design high performance and energy-efficient NoC architectures. In this paper, we propose a 3D stacked NoC router architecture, called MIRA, which unlike the 3D routers in previous works, is stacked into multiple layers and optimized to reduce the overall area requirements and power consumption. We discuss the design details of a four-layer 3D NoC and its enhanced version with additional express channels, and compare them against a (6×6) 2D design and a baseline 3D design. All the designs are evaluated using a cycle-accurate 3D NoC simulator, and integrated with the Orion power model for performance and power analysis. The simulation results with synthetic and application traces demonstrate that the proposed multi-layered NoC routers can outperform the 2D and naïve 3D designs in terms of performance and power. It can achieve up to 42% reduction in power consumption and up to 51% improvement in average latency with synthetic workloads. With real workloads, these benefits are around 67% and 38%, respectively.

show abstract

Section: D Integration Techniquesmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

MIRA: A Multi-layered On-Chip Interconnect Router Architecture

Park

Eachempati

Das

et al. 2008

2008 International Symposium on Computer Architecture

View full text Add to dashboard Cite

show abstract

“…Weaver et al [36] proposed to selectively squash instructions when long delays are encountered to reduce IQ soft error vulnerability. Madan et al [13] proposed several mechanisms to save power in redundant multithreading (RMT), later in [14], they leveraged 3D technologies to tolerate soft errors. Walcott et al [37] used a set of processor metrics to predict structure AVF, which is then applied to trigger RMT for structure's reliability maintenance.…”

Section: Related Workmentioning

confidence: 99%

Optimizing Issue Queue Reliability to Soft Errors on Simultaneous Multithreaded Architectures

Zhang

et al. 2008

2008 37th International Conference on Parallel Processing

View full text Add to dashboard Cite

The issue queue (IQ) is a key microarchitecture structure for exploiting instruction-level and thread-level parallelism in dynamically scheduled simultaneous multithreaded (SMT) processors. However, exploiting more parallelism yields high susceptibility to transient faults on a conventional IQ. With the rapidly increasing soft error rates, the IQ is likely to be a reliability hot-spot on SMT processors fabricated with advanced technology nodes using smaller and denser transistors with lower threshold voltages and tighter noise margins. In this paper, we explore microarchitecture techniques to optimize IQ reliability to soft error on SMT architectures. We propose to use off-line instruction vulnerability profiling to identify reliability critical instructions. The gathered information is then used to guide reliability-aware instruction scheduling and resource allocation in multithreaded execution environments. We evaluate the efficiency of the proposed schemes across various SMT workload mixes. Extensive simulation results show that, on average, our microarchitecture level soft error mitigation techniques can significantly reduce IQ vulnerability by 42% with 1% performance improvement. To maintain runtime IQ reliability for pre-defined thresholds, we propose dynamic vulnerability management (DVM) mechanisms. Experimental results show that our DVM techniques can effectively achieve desired reliability/performance tradeoffs.

show abstract

“…We expand previous work on timing uncertainty measurements [2] by deploying the Vernier TDC structure with modifications to support measurements in 3D. The snapon, plug-and-play feature of 3D stacking has been previously proposed for stackable processor design [3], fault-tolerance improvement [4] and software introspection [5].…”

Section: Introductionmentioning

confidence: 99%

Leveraging 3D-IC for on-chip timing uncertainty measurements

Widialaksono

Zhao

Davis

et al. 2014

2014 International 3D Systems Integration Conference (3DIC)

View full text Add to dashboard Cite

Modern high-performance designs require accurate on-chip timing uncertainty measurements for post-silicon validation of high speed interfaces and clock distribution networks. On-chip timing measurements capabilities must keep up with growing design complexity and process variations to meet competitive product time-to-market. However, enhancing silicon debug capabilities cannot simply be met by proliferating on-chip structures, since the overhead would be prohibitively expensive to deploy. We propose moving on-chip debug and validation structures onto a separate die which would be stacked onto the product die using three-dimensional integration (3D-IC). This paper focuses on achieving observability at clock sinks which are critical for understanding on-chip timing uncertainty. We present a circuit implementation and design flow which realizes high volume on-chip timing measurements for a 2D product die.

show abstract

Leveraging 3D Technology for Improved Reliability

Abstract: Abstract

Cited by 8 publications

References 32 publications

MIRA: A Multi-layered On-Chip Interconnect Router Architecture

MIRA: A Multi-layered On-Chip Interconnect Router Architecture

Optimizing Issue Queue Reliability to Soft Errors on Simultaneous Multithreaded Architectures

Leveraging 3D-IC for on-chip timing uncertainty measurements

Contact Info

Product

Resources

About