2016
DOI: 10.1109/ted.2016.2613142
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Intertwined Design: A Novel Lithographic Method to Realize Area Efficient High-Voltage SiC BJTs and Darlington Transistors

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Cited by 6 publications
(2 citation statements)
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“…It is critical to boost the gain of RFAs for loss compensation and signal conditioning while maintaining a compact form factor and low complexity. To improve the gain of an RFA, various circuit topologies, such as a cascode configuration and Darlington structure, have been proposed in the literature [6][7][8][9][10]. The cascode topology provides increased output resistance that leads to a higher output voltage, and increased isolation between the input and output ports, which simplifies the design of the matching network and reduces the Miller effect, at the cost of a higher power supply.…”
Section: Introductionmentioning
confidence: 99%
“…It is critical to boost the gain of RFAs for loss compensation and signal conditioning while maintaining a compact form factor and low complexity. To improve the gain of an RFA, various circuit topologies, such as a cascode configuration and Darlington structure, have been proposed in the literature [6][7][8][9][10]. The cascode topology provides increased output resistance that leads to a higher output voltage, and increased isolation between the input and output ports, which simplifies the design of the matching network and reduces the Miller effect, at the cost of a higher power supply.…”
Section: Introductionmentioning
confidence: 99%
“…SiC bipolar junction transistors (BJTs) are promising power devices due to their low forward-voltage drop for high temperature, high frequency and radiation hardened application. Furthermore, the related integrated circuits of SiC BJTs are also under development [1][2][3][4]. Compared with SiC MOSFETs, SiC BJTs have no critical problems of gate oxide reliability and low channel mobility.…”
Section: Introductionmentioning
confidence: 99%