Integration of copper with low-k dielectrics for 0.13 μm technology

Gambino, Jeff; Stamper, A. K.; McDevitt, T.L.; McGahay, V.; Luce, S.; Pricer, Timothy J.; Porth, B.; Senowitz, Corey; Kontra, R.; Gibson, M.; Wildman, H.; Piper, A.; Benson, Charles; Standaert, T.; Biolsi, Peter; Cooney, E.

doi:10.1109/ipfa.2002.1025628

Cited by 11 publications

(5 citation statements)

References 6 publications

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“…Initially, SiO 2 was used as the interlevel dielectric surrounding the Cu wires (Figure 8.7; [202] For process integration, SiO 2 has many good properties [22][23][24]. It is thermally and chemically stable and therefore does not degrade during processing.…”

Section: Low-k Dielectricsmentioning

confidence: 99%

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Process Technology for Copper Interconnects

Gambino

2012

Handbook of Thin Film Deposition

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Section: Low-k Dielectricsmentioning

confidence: 99%

“…23 Resistance versus time data during stress migration test for M3-V2-M2 via chain for samples with or without postmetal annealing[143].…”

mentioning

confidence: 99%

Process Technology for Copper Interconnects

Gambino

2012

Handbook of Thin Film Deposition

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“…2). For process integration, SiO 2 has many good properties [3,4]. It is thermally and chemically stable, and therefore does not degrade during processing.…”

Section: Low-k Dielectricsmentioning

confidence: 99%

Process Challenges for Integration of Copper Interconnects with Low-k Dielectrics

Gambino¹

2011

ECS Trans.

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Copper interconnects have gained wide acceptance in the microelectronics industry due to improved resistivity and reliability compared to Al interconnects. Initially SiO2 was used as the interlevel dielectric. To reduce interconnect capacitance, C-doped SiO2 or SiCOH was introduced at the 90 nm node, and porous SiCOH was introduced at the 45 nm node, to achieve a dielectric constant of 2.5 or less. However, there are many process problems with the integration of Cu interconnects and porous low-k dielectrics, including patterning, liner coverage, chemical mechanical polishing (CMP), and packaging. In this paper, some of the key integration challenges are discussed.

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“…Copper interconnects and vias are formed using a dual damascene process (1,24). The first step is deposition of the interlevel dielectric, followed by patterning of vias and trenches, that are etched into the dielectric.…”

Section: The Effect Of Processing On Stress-induced Voidsmentioning

confidence: 99%

Reliability of Copper Interconnects: Stress-Induced Voids

Gambino

Lee²,

Chen³

et al. 2009

ECS Trans.

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Stress-induced voids can form in Cu interconnects, due to either thermal expansion mismatch between the metal and the dielectric or due to confined grain growth in the Cu. The fail rate due to stress-induced voids increases as device dimensions decrease, because the critical void size to cause a fail decreases. Good process control is required for trench and via profiles, barrier and seed layer coverage, Cu fill, and cap layer adhesion, to prevent fails from stress-induced voids.

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Integration of copper with low-k dielectrics for 0.13 μm technology

Cited by 11 publications

References 6 publications

Process Technology for Copper Interconnects

Process Technology for Copper Interconnects

Process Challenges for Integration of Copper Interconnects with Low-k Dielectrics

Reliability of Copper Interconnects: Stress-Induced Voids

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