Reliability of Copper Interconnects: Stress-Induced Voids

Abstract

Stress-induced voids can form in Cu interconnects, due to either thermal expansion mismatch between the metal and the dielectric or due to confined grain growth in the Cu. The fail rate due to stress-induced voids increases as device dimensions decrease, because the critical void size to cause a fail decreases. Good process control is required for trench and via profiles, barrier and seed layer coverage, Cu fill, and cap layer adhesion, to prevent fails from stress-induced voids.

Copper Metal for Semiconductor Interconnects

“…On the other hand, the failure rate for stress-induced void in Cu line increases with increasing line width ( Figure 10) opposite to what is observed with Al line [116,117,122]. Two mechanisms can explain this unique behavior.…”

“…Failure rate of stress-induced void versus M2 line width and V2 via size after annealing stress at 225 C for 1000 h. Reproduced with permission from Ref. [122].…”

“…The operation timing is after Cu plating and before Cu CMP step. It is noted that the maximum annealing temperature must be limited after dielectric capping layer deposition because high-temperature annealing after dielectric capping layer deposition can lead to high rates of stress-induced void formation due to either confined grain growth or due to increased stress in the Cu line [122,132]. Additionally, the use of metal capping layers [133] and/or Cu alloying lines [106,107], which are used to improve EM has also shown to reduce the failure rate of stress-induced void.…”