The ability to deposit and tailor reliable semiconducting films (with a particular recent emphasis on ultrathin systems) is indispensable for contemporary solid-state electronics. The search for thin-film semiconductors that provide simultaneously high carrier mobility and convenient solution-based deposition is also an important research direction, with the resulting expectations of new technologies (such as flexible or wearable computers, large-area high-resolution displays and electronic paper) and lower-cost device fabrication. Here we demonstrate a technique for spin coating ultrathin (approximately 50 A), crystalline and continuous metal chalcogenide films, based on the low-temperature decomposition of highly soluble hydrazinium precursors. We fabricate thin-film field-effect transistors (TFTs) based on semiconducting SnS(2-x)Se(x) films, which exhibit n-type transport, large current densities (>10(5) A cm(-2)) and mobilities greater than 10 cm2 V(-1) s(-1)--an order of magnitude higher than previously reported values for spin-coated semiconductors. The spin-coating technique is expected to be applicable to a range of metal chalcogenides, particularly those based on main group metals, as well as for the fabrication of a variety of thin-film-based devices (for example, solar cells, thermoelectrics and memory devices).

The issue of stress in thin films and functional coatings is a persistent problem in materials science and technology that has congregated many efforts, both from experimental and fundamental points of view, to get a better understanding on how to deal with, how to tailor, and how to manage stress in many areas of applications. With the miniaturization of device components, the quest for increasingly complex film architectures and multiphase systems and the continuous demands for enhanced performance, there is a need toward the reliable assessment of stress on a submicron scale from spatially resolved techniques. Also, the stress evolution during film and coating synthesis using physical vapor deposition (PVD), chemical vapor deposition, plasma enhanced chemical vapor deposition (PECVD), and related processes is the result of many interrelated factors and competing stress sources so that the task to provide a unified picture and a comprehensive model from the vast amount of stress data remains very challenging. This article summarizes the recent advances, challenges, and prospects of both fundamental and applied aspects of stress in thin films and engineering coatings and systems, based on recent achievements presented during the 2016 Stress Workshop entitled “Stress Evolution in Thin Films and Coatings: from Fundamental Understanding to Control.” Evaluation methods, implying wafer curvature, x-ray diffraction, or focused ion beam removal techniques, are reviewed. Selected examples of stress evolution in elemental and alloyed systems, graded layers, and multilayer-stacks as well as amorphous films deposited using a variety of PVD and PECVD techniques are highlighted. Based on mechanisms uncovered by in situ and real-time diagnostics, a kinetic model is outlined that is capable of reproducing the dependence of intrinsic (growth) stress on the grain size, growth rate, and deposited energy. The problems and solutions related to stress in the context of optical coatings, inorganic coatings on plastic substrates, and tribological coatings for aerospace applications are critically examined. This review also suggests strategies to mitigate excessive stress levels from novel coating synthesis perspectives to microstructural design approaches, including the ability to empower crack-based fabrication processes, pathways leading to stress relaxation and compensation, as well as management of the film and coating growth conditions with respect to energetic ion bombardment. Future opportunities and challenges for stress engineering and stress modeling are considered and outlined.

We identified a family of materials which can be directly electroplated with Cu in acidic plating baths commonly found in the microelectronics industry. Details are presented illustrating a number of important properties of the electroplated Cu/linear material system. These include the adhesion of the plated film to liner material, the recrystallization behavior of the plated film, the texture of the plated film, and the resistivity of the plated film after high-temperature anneals. Finally, an example is presented illustrating the direct plating of Cu across an 8 in. wafer without the use of a Cu seed layer.

Solution-processed thin-film semiconductors may offer a route to low-cost and flexible thin-film transistors (TFTs) with performance sufficient for applications such as large area displays, wearable computers, radio frequency identification tags, and paperlike displays. [1][2][3] Transistors incorporating soluble organic and polymeric semiconducting thin films have been demonstrated with field-effect hole mobilities of up to ∼1 cm 2 /(V‚s), 4,5 comparable to amorphous silicon TFTs, and lower electron mobilities on the order of 10 -2 cm 2 /(V‚s). [6][7][8][9] Likewise, hybrid organic-inorganic materials maintain the processibility of organic semiconductors while carrying current in an inorganic network to achieve hole mobilities of ∼1 cm 2 /(V‚s). 10,11 More recently, solutionprocessed inorganic semiconductors, based on nanomaterials 12,13 or molecular precursors, 14,15 have emerged as an alternative capable of even higher performance. Metal chalcogenide TFTs have been fabricated using low temperature (T e 350 °C) solution processing, exhibiting electron mobilities in the range of 10-20 cm 2 /(V‚s). 14,15 High performance amorphous oxide flexible transistors have also recently been produced at room temperature by pulsed laser deposition, retaining some benefits of solution processing and yielding electron mobilities of 6-9 cm 2 /(V‚s). 16 These results expand the range of potential applications for flexible and/or solution-processed transistors by approaching the performance of polycrystalline silicon. However, analogous p-type devices, required for complementary logic or p-n heterojunctions, have not been demonstrated to date. We report the first p-type TFTs with spin-cast all-inorganic channels. The hydrazine-precursor method used previously for binary n-type compounds 14,15 is modified and extended to prepare thin films of the ternary (bimetallic) compound copper indium diselenide (CuInSe 2 ). As CuInSe 2 is also a candidate for application in photovoltaic cells, alternative

Superconducting qubits are sensitive to a variety of loss mechanisms including dielectric loss from interfaces. By changing the physical footprint of the qubit it is possible to modulate sensitivity to surface loss. Here we show a systematic study of planar superconducting transmons of differing physical footprints to optimize the qubit design for maximum coherence. We find that qubits with small footprints are limited by surface loss and that qubits with large footprints are limited by other loss mechanisms which are currently not understood.