Integrated Deep Trench Capacitor in Si Interposer for CoWoS Heterogeneous Integration

Hou, S. Y.; Wu, Cheng‐Hsien; Yu, Douglas; Hsia, H.; Tsai, Chien‐Hsiung; Ting, Kong; Yu, Tianjun; Lee, Y.W.; Chen, F.C.; Chiou, W.C.; Wang, C.T.

doi:10.1109/iedm19573.2019.8993498

Cited by 33 publications

(5 citation statements)

References 8 publications

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“…the insulator would be beneficial by introducing 2D or 3D structures employed in the micro-batteries and -capacitors. 11,[20][21][22][23] These points are also beyond the scope of this work and will be reported in a future study.…”

Section: Journal Of Applied Physicsmentioning

confidence: 99%

“…[1][2][3] Among them, battery and supercapacitor 4,5 are attractive for applications, such as electric vehicles and renewable energy sources. Additionally, the miniaturization of storage devices such as micro-battery [6][7][8] and -capacitor 9 is of importance and has been studied for the system-on-chip (SoC), 7,[10][11][12] internet-of-things, medical, flexible, and wearable devices. 13 In terms of the batteries, the Li-ion battery is leading the storage devices.…”

Section: Introductionmentioning

confidence: 99%

“…Furthermore, the Si-based 3D capacitor has been studied in the applications of SoC and system-in-package to supply stable electric power for a decade. 11,[20][21][22][23] As categorized in the Ragone plot, however, a simple capacitor supplies the high electric power rather than the energy, whereas the battery has opposite properties. It is because the conventional capacitor shows a linear dependence between stored charge and output voltage and is regarded as a small storable energy.…”

Section: Introductionmentioning

confidence: 99%

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Potential application of p–i–n semiconductor capacitor with non-linear voltage–charge characteristic for secondary battery

Yoshida

Sano

2020

Journal of Applied Physics

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We carried out the time-dependent drift-diffusion simulation to study a capacitor with semiconductor electrodes and its potential application for a battery-like operation. We employed the p-i-n and p-n structures with an insulator inserted in the middle of the devices. Both devices can store and retain the charge and voltage without any degradation, thanks to the insulator which inhibits carrier recombination. Additionally, they have a strong non-linear dependence between the stored charge and voltage, whereas a conventional capacitor shows linearity. The non-linearity is induced as follows. The junction capacitance dominates under smaller bias than the built-in potential. When the voltage exceeds the built-in, the capacitance associated with the insulator characterizes the charge-voltage relation. The intrinsic layer further enhances the non-linearity and keeps the output voltage high until the stored charge becomes significantly small due to its small capacitance. As a result, the p-i-n like structure with the insulator stores larger energy than that of the conventional capacitor and realizes the battery-like operation.

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Section: Journal Of Applied Physicsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Potential application of p–i–n semiconductor capacitor with non-linear voltage–charge characteristic for secondary battery

Yoshida

Sano

2020

Journal of Applied Physics

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“…Through-silicon-vias (TSVs), the biggest feature of 3D-SICs, enable vertical signal transfer among stacked ICs which enhances performance and energy by optimized signal lines between stacked ICs [8][9][10][11][12][13]. Although wider signal bus is required for enormous scale data transfer, densely manufactured signal bus needs to solve crosstalk among the channels [14][15][16][17][18][19][20] as well as power line noise [21][22][23][24][25][26][27]. To avoid bit error caused by such crosstalk, it requires frequency or voltage optimization that cause additional issues like lower data transfer speed or larger power consumption, respectively [28,29].…”

Section: Introductionmentioning

confidence: 99%

Analysis and evaluation of noise coupling between through-silicon-vias

Araga

Watanabe

Shimamoto

et al. 2021

IEICE Electron. Express

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Three-dimensional stacking of ICs with through-silicon-vias (TSVs) is one of the most expected way to integrate an enormous scale system in a small footprint. Shortened distance and expanded interconnect area are proofed to enable low-power, ultra-wide bandwidth communication among logic, memory, and analog component. In the 3-D integrated system with massive vertical interconnects, noise coupling among TSVs can be problem, by degrading signal integrity. We made a simple model to estimate noise coupling among TSVs and analyzed the coupling strength against parasitic capacitance of liner oxide. A test chip is fabricated, and the noise coupling strength is evaluated through on-chip waveform capturing circuitry. The analytical result and measured result show good consistency, and they indicate smaller size TSVs show better noise isolation characteristics as well as process simplicity.

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“…Tactically deployed for decades 5,6 , this approach using chiplets-smaller chips that when packaged together realize the function of a larger chip-can meet ever-increasing compute demands and overcome die reticle limits and yield challenges in advanced process nodes. Rapid progress in advanced packaging technology [7][8][9][10][11][12] has allowed designers to interconnect chiplets on-package and keep Moore's law 13 going.…”

mentioning

confidence: 99%

High-performance, power-efficient three-dimensional system-in-package designs with universal chiplet interconnect express

Das Sharma,

Pasdast,

Tiagaraj

et al. 2024

Nat Electron

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Universal chiplet interconnect express (UCIe) is an open industry standard interconnect for a chiplet ecosystem in which chiplets from multiple suppliers can be packaged together. The UCIe 1.0 specification defines interoperability using standard and advanced packaging technologies with planar interconnects. Here we examine the development of UCIe as the bump interconnect pitches reduce with advances in packaging technologies for three-dimensional integration of chiplets. We report a die-to-die solution for the continuum of package bump pitches down to 1 µm, providing circuit architecture details and performance results. Our analysis suggests that—contrary to trends seen in traditional signalling interfaces—the most power-efficient performance for these architectures can be achieved by reducing the frequency as the bump pitch goes down. Our architectural approach provides power, performance and reliability characteristics approaching or exceeding that of a monolithic system-on-chip design as the bump pitch approaches 1 µm.

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Integrated Deep Trench Capacitor in Si Interposer for CoWoS Heterogeneous Integration

Cited by 33 publications

References 8 publications

Potential application of p–i–n semiconductor capacitor with non-linear voltage–charge characteristic for secondary battery

Potential application of p–i–n semiconductor capacitor with non-linear voltage–charge characteristic for secondary battery

Analysis and evaluation of noise coupling between through-silicon-vias

High-performance, power-efficient three-dimensional system-in-package designs with universal chiplet interconnect express

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