This article presents a cryptographic key protection technique from physical security attacks through Si-backside of IC chip. Flip-chip packaging leads to a serious security hole that allows emerging backside physical security attacks. The proposed backside buried metal (BBM) structure forming a meander wire pattern on the Si-backside detects unexpected disconnection of the meander and warns the malicious attempts to expose a vulnerable Si substrate. Moreover, the BBM meander also shields key information of cryptographic circuit from both passive side-channel attacks and active laser fault injection as well. Unlike other conventional laminate-based protection, this backside monolithic approach does not require frontside wiring resources or additional packaging layers, resulting in only 0.0025% size-overhead. The BBM meander was formed on the backside of a 0.13-µm CMOS cryptographic chip by wafer-level via-last BBM processing.
The superior noise reduction performance of an in-stack decoupling capacitor (DECAP) is demonstrated. A three-tier stacked demonstrator is manufactured with an ultrawide data bus that connects a top memory chip and a bottom logic chip. An in-stack evaluation circuitry on a middle tier (Si interposer) captures voltage variation waveforms during chip-to-chip data communication. In-stack DECAPs in arrays on a Si interposer and discrete ceramic capacitors on an organic interposer of a ball-grid array package are compared. Silicon measurements with an in-stack noise monitoring technique show that the DECAPs on the Si interposer more locally shunt out the AC components of power supply current over a wider frequency range than the capacitors on the package interposer.
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