3-D CMOS Chip Stacking for Security ICs Featuring Backside Buried Metal Power Delivery Networks With Distributed Capacitance

Monta, Kazuki; Sonoda, Hiroki; Okidono, Takaaki; Araga, Yuuki; Watanabe, Naoya; Shimamoto, H.; Kikuchi, Katsuya; Miura, Noriyuki; Miki, Takuji; Nagata, Makoto

doi:10.1109/ted.2021.3058226

Cited by 16 publications

(9 citation statements)

References 17 publications

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“…5. In addition, the collection of EM waves on PCB was suggested the mitigation of power SC leakage [31].…”

Section: Attack Protections -Secure Packagingmentioning

confidence: 99%

Design of Circuits and Packaging Systems for Security Chips

Nagata

2023

IEICE Trans. Electron.

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Hardware oriented security and trust of semiconductor integrated circuit (IC) chips have been highly demanded. This paper outlines the requirements and recent developments in circuits and packaging systems of IC chips for security applications, with the particular emphasis on protections against physical implementation attacks. Power side channels are of undesired presence to crypto circuits once a crypto algorithm is implemented in Silicon, over power delivery networks (PDNs) on the frontside of a chip or even through the backside of a Si substrate, in the form of power voltage variation and electromagnetic wave emanation. Preventive measures have been exploited with circuit design and packaging technologies, and partly demonstrated with Si test vehicles.

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“…5. In addition, the collection of EM waves on PCB was suggested the mitigation of power SC leakage [31].…”

Section: Attack Protections -Secure Packagingmentioning

confidence: 99%

Design of Circuits and Packaging Systems for Security Chips

Nagata

2023

IEICE Trans. Electron.

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“…This structure obviates SC leakages vertically by the BBM shielding effects while horizontally by the BBM distributed decoupling capacitors over the PDNs. The latter flattens the change of power currents locally among logic switching gates and therefore suppresses the power current dependence on arithmetic computation sequences in such as EC-based public-key crypto algorithms [87].…”

Section: Secure Packagingmentioning

confidence: 99%

Physical Attack Protection Techniques for IC Chip Level Hardware Security

Nagata

Miki

Miura

2022

IEEE Trans. VLSI Syst.

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“…Figure 10 depicts a 3D secure packaging structure. 34,35) All IO pads of each chip are vertically connected to the BBM of the upper tier formed on the backside of the chip via through-silicon vias and microbumps. The BBM also forms a power and ground wiring network; thus, a MOS capacitance is formed between the BBM and the Si substrate via SiO 2 .…”

Section: Detection Of Si-backside Attacksmentioning

confidence: 99%

Countermeasures against physical security attacks on ICs utilizing on-chip wideband ADCs

Miki

Nagata

2022

Jpn. J. Appl. Phys.

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Cryptographic ICs on edge devices for internet-of-things (IoT) applications are exposed to an adversary and threatened by malicious side channel analysis. On-chip analog monitoring by sensor circuits embedded inside the chips is one of the possible countermeasures against such attacks. An on-chip monitor circuit consisting of a successive approximation register (SAR) analog-to-digital converter (ADC) and an input buffer acquires a wideband signal, which enables to detects an irregular noise due to an active fault injection and a passive side channel leakage analysis. In this paper, several countermeasures against security attacks utilizing wideband on-chip monitors are reviewed. Each technique is implemented on a prototype chip, and the measurement results prove they can effectively detect and diagnose the security attacks.

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3-D CMOS Chip Stacking for Security ICs Featuring Backside Buried Metal Power Delivery Networks With Distributed Capacitance

Cited by 16 publications

References 17 publications

Design of Circuits and Packaging Systems for Security Chips

Design of Circuits and Packaging Systems for Security Chips

Physical Attack Protection Techniques for IC Chip Level Hardware Security

Countermeasures against physical security attacks on ICs utilizing on-chip wideband ADCs

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