Physical Attack Protection Techniques for IC Chip Level Hardware Security

Nagata, Makoto; Miki, Takuji; Miura, Noriyuki

doi:10.1109/tvlsi.2021.3073946

Cited by 24 publications

(9 citation statements)

References 88 publications

(66 reference statements)

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“…We recommend watch developers to activate flash memory protection functions offered by the microcontroller manufacturer to protect sensitive data from straightforward memory dump through debug interface. To protect against invasive data extraction, we recommend backside shielding [17], [18] or sensing techniques [19] to deter invasive sample preparation.…”

Section: Discussionmentioning

confidence: 99%

Security Evaluation of Microcontrollers: A Case Study in Smart Watches

Zeng,

Liu,

Chua

et al. 2023

2023 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)

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Smart watches contain sensitive information like application software, user health and fitness data. Some of these data are often stored in embedded flash memory in microcontrollers. Here we explore two flash memory reading techniques to evaluate data security in smart watches against hardware attacks. One technique is the common approach of logical data acquisition, which is non-invasive and access the data through debug interface. It dumps the whole flash memory content based on its logical address. The other technique is a new selective staining approach. It extracts data directly from memory cells and requires invasive sample preparation. It extracts all binary bits in the flash memory based on its physical address. These two techniques are complementary to one another and ensure the accuracy of extracted memory content. The nature of data in the flash memory was confirmed by comparing the data between a new and a used watch. Majority of the flash memory was used for application software, with a small region found reserved to store the last shutdown information of the watch.

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Section: Discussionmentioning

confidence: 99%

Security Evaluation of Microcontrollers: A Case Study in Smart Watches

Zeng,

Liu,

Chua

et al. 2023

2023 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)

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“…This translates into at least five to six orders of magnitude heavier attack effort [91], [92], as evidence of the effectiveness of physical-level counteraction. As an alternative approach to be used when routing discipline is not acceptable, active techniques for EM probe detection have also been demonstrated [93]. In detail, the EM probe detection circuit in [94] is based on a fully-digital sensor circuit with reference-free dual-coil sensing, as well as a ring-oscillator-based sensor calibration with percentage point-range area overhead and intermittent operation for lower power.…”

Section: On-chip Sensorization For Non-invasive Physical Attack Detec...mentioning

confidence: 99%

Aggressive Design Reuse for Ubiquitous Zero-Trust Edge Security—From Physical Design to Machine-Learning-Based Hardware Patching

Alioto

2023

IEEE Open J. Solid-State Circuits Soc.

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This work presents an overview of challenges and solid pathways towards ubiquitous and sustainable hardware security in next-generation silicon chips at the edge of distributed and connected systems (e.g., IoT, AIoT). As first challenge, the increasingly connected nature and the exponential proliferation of edge devices is unabatingly increasing the overall attack surface, making attacks easier and mandating ubiquitous security down to each edge node. At the same time, the necessity to incorporate zero-trust policies in large-scale distributed systems requires a complete set of security primitives for hardware-backed authentication, and a higher degree of physical context awareness (including primitives detecting the onset of physical attacks). Thus, making the inclusion of such security primitives economically sustainable even in low-end devices is a second key challenge. As third challenge, the ever-changing vulnerability landscape and the need for increased chip longevity in distributed systems requires security assurance methods that are sustainable and adaptive across the entire chip lifecycle. In this work, design principles and promising directions to enable ubiquitous and sustainable security capabilities along with physical awareness are discussed. Such achievements require a fundamental rethinking of design methodologies to enable aggressive design and resource reuse (e.g., area, power, design effort), along with low-cost on-chip sensorization and intelligence for physical attack detection. Such rethinking inevitably crosses over the traditional design abstractions, and requires innovation from the physical to the algorithmic level. At the physical and circuit level, design and resource reuse is enabled by immersed-inlogic and in-memory security approaches. At the algorithm level, "hardware patching" is introduced and exemplified to show that run-time intelligence (machine learning) allows security capabilities to adapt and improve over time, as typical of security patching in software. Sensing techniques to detect attacks in situ from non-invasive to invasive are illustrated, while still preserving fully-automated design approaches. Overall, the above design principles are expected to push security capabilities in distributed systems to a new level, ultimately making the edge more intelligent and self-reliant, and security measures more distributed.

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“…On the Why SC leakages are observable from the Si backsideits answer is explained with a general sketch of a power delivery network (PDN) system shown in Fig. 5 [21]. An external power source supplies an IC chip, where power lines are in series connected through PCBs, packages, and IC chips.…”

Section: Attack Surfaces -Power and Em Sc Leakagesmentioning

confidence: 99%

Design of Circuits and Packaging Systems for Security Chips

Nagata

2023

IEICE Trans. Electron.

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Hardware oriented security and trust of semiconductor integrated circuit (IC) chips have been highly demanded. This paper outlines the requirements and recent developments in circuits and packaging systems of IC chips for security applications, with the particular emphasis on protections against physical implementation attacks. Power side channels are of undesired presence to crypto circuits once a crypto algorithm is implemented in Silicon, over power delivery networks (PDNs) on the frontside of a chip or even through the backside of a Si substrate, in the form of power voltage variation and electromagnetic wave emanation. Preventive measures have been exploited with circuit design and packaging technologies, and partly demonstrated with Si test vehicles.

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Physical Attack Protection Techniques for IC Chip Level Hardware Security

Cited by 24 publications

References 88 publications

Security Evaluation of Microcontrollers: A Case Study in Smart Watches

Security Evaluation of Microcontrollers: A Case Study in Smart Watches

Aggressive Design Reuse for Ubiquitous Zero-Trust Edge Security—From Physical Design to Machine-Learning-Based Hardware Patching

Design of Circuits and Packaging Systems for Security Chips

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