Improving the subthreshold performance of junctionless transistor using spacer engineering

Saini, Gaurav; Choudhary, Sudhanshu

doi:10.1016/j.mejo.2016.11.012

Cited by 13 publications

(5 citation statements)

References 14 publications

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“…The small SS is required to provide a faster transition between I ON to I OFF . 21,22 The Proposed device shows near ideal subthreshold slope 70.187 mV dec −1 in linear region and, 71.512 mV dec −1 in saturation region respectively shown in Fig. 5b.…”

Section: Simulation Of Device and Discussionmentioning

confidence: 82%

Ferroelectric Based Low Power MOSFET for DC/RF Applications: Machine Learning Assisted Statistical Variation Analysis

Singh,

Baghel,

Tirkey

2024

ECS J. Solid State Sci. Technol.

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The analog/radio-frequency (RF) performance of a ferroelectric-based substrate metal oxide semiconductor field effect transistor (FE-MOSFET) with dielectric spacer was designed and proposed. The utilization of gate side wall spacers aims to mitigate short-channel effects (SCEs), and improve overall device performance. Simulation results demonstrate enhanced performance metrics, including improved transconductance (80%), reduced gate leakage (95.4%), and enhanced cutoff frequency (25%), making this design a promising candidate for next-generation high-performance analog and RF applications. Additionally, a novel machine learning (ML)-assisted approach is proposed for investigating the spacer-based FE-MOSFET to reduce the computational cost of numerical TCAD device simulations with the help of conventional- artificial neural network (C-ANN). This method is reported for the first-time ML-based C-ANN for Fe-based low-power MOSFET, matches the similar accuracy of physics-based TCAD with the fastest learning rate and fastest computational speed (in 95-100 seconds). An ML-based prediction replacement for physics-based TCAD is developed to save around 8-10 hours of runtime for each iteration. Because ML predictions can never be 100% accurate, it is essential to ensure approximately zero mean-square error in the final results.

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Section: Simulation Of Device and Discussionmentioning

confidence: 82%

Ferroelectric Based Low Power MOSFET for DC/RF Applications: Machine Learning Assisted Statistical Variation Analysis

Singh,

Baghel,

Tirkey

2024

ECS J. Solid State Sci. Technol.

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“…This design choice implies a more complex fabrication process with respect to the bulk structure [5]. The designer could follow different approaches in order to optimize junctionless FinFETs: work function engineering of the gate to reduce I o f f (by changing the gate work function from 4.5 eV to 5.4 eV, I o f f can be reduced by five order of magnitudes) [7]; spacer engineering to improve performance (e.g., dual-k spacers architecture can provide an improvement in I on by 72.5% and in DIBL by 37.8%) [9]; doping engineering by using a Gaussian doped channel, which can lead to an increase in I on by 21.1% [10,13], or a lightly doped channel, which allows for better gate control on the device [11]; gate oxide engineering to provide higher performance (in terms of I on /I o f f and DIBL) by the implementation of complex hetero gate oxide structures [8]. For example, the double hetero gate oxide (DHGO) presented in Figure 9 can obtain a higher I on /I o f f with respect to conventional and triple/quadruple hetero gate oxide (THGO/QHGO) structures.…”

Section: Finfetmentioning

confidence: 99%

Junctionless Transistors: State-of-the-Art

2020

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Recent advances in semiconductor technology provide us with the resources to explore alternative methods for fabricating transistors with the goal of further reducing their sizes to increase transistor density and enhance performance. Conventional transistors use semiconductor junctions; they are formed by doping atoms on the silicon substrate that makes p-type and n-type regions. Decreasing the size of such transistors means that the junctions will get closer, which becomes very challenging when the size is reduced to the lower end of the nanometer scale due to the requirement of extremely high gradients in doping concentration. One of the most promising solutions to overcome this issue is realizing junctionless transistors. The first junctionless device was fabricated in 2010 and, since then, many other transistors of this kind (such as FinFET, Gate-All-Around, Thin Film) have been proposed and investigated. All of these semiconductor devices are characterized by junctionless structures, but they differ from each other when considering the influence of technological parameters on their performance. The aim of this review paper is to provide a simple but complete analysis of junctionless transistors, which have been proposed in the last decade. In this work, junctionless transistors are classified based on their geometrical structures, analytical model, and electrical characteristics. Finally, we used figure of merits, such as I o n / I o f f , D I B L , and S S , to highlight the advantages and disadvantages of each junctionless transistor category.

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“…Recently, the signi cant reduction in power has been examined in performance of JLT has been improved using spacer engineering. Dual-κ spacer length was optimized to improve the subthreshold performance [18]. Impact of Spacer extension length (L ext ) and placement of spacers on only drain side, both sides, only source side on Trigate FET was explored by [19] to enhance the analog performance.…”

Section: Introductionmentioning

confidence: 99%

Performance Evaluation of Junctionless FinFET using Spacer Engineering at 15 nm Gate Length

Kaur

Gill

Kaur

2022

Silicon

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In this proposed work, performance of junctionless transistor with the use of spacers has been evaluated at 15nm gate length in Cogenda TCAD tool. This work is implemented as variation in four parts: changing the spacer extension length, placement of spacers having dual-κ, proportion of low and high-κ spacers, and value of high-κ dielectric constant. Impact of all these parameters is considered on the output of proposed device in terms of various output parameters like on-current (I ON ), off-current (I OFF ), subthreshold swing (SS), drain induced barrier lowering (DIBL), transconductance (g m ), transconductance generation factor (TGF), output conductance (g d ), early voltage (V ea ) and intrinsic gain (A v ). From the simulations, it has been observed that placing spacers of dual-κ along the left and right sides of gate region has improved device performance in terms of output parameters. Due to increased gate capacitances, the increase in dielectric constant value has degraded the device performance for longer spacer extension length. However, for shorter spacer extension length, the device characteristics are improved as the value of dielectric constant is increased. Therefore a trade-off is required to get the optimum results of the device. Parameters κ=15Source side Both sides Drain side

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Improving the subthreshold performance of junctionless transistor using spacer engineering

Cited by 13 publications

References 14 publications

Ferroelectric Based Low Power MOSFET for DC/RF Applications: Machine Learning Assisted Statistical Variation Analysis

Ferroelectric Based Low Power MOSFET for DC/RF Applications: Machine Learning Assisted Statistical Variation Analysis

Junctionless Transistors: State-of-the-Art

Performance Evaluation of Junctionless FinFET using Spacer Engineering at 15 nm Gate Length

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