Abstract:In this proposed work, performance of junctionless transistor with the use of spacers has been evaluated at 15nm gate length in Cogenda TCAD tool. This work is implemented as variation in four parts: changing the spacer extension length, placement of spacers having dual-κ, proportion of low and high-κ spacers, and value of high-κ dielectric constant. Impact of all these parameters is considered on the output of proposed device in terms of various output parameters like on-current (I ON ), off-current (I OFF ),… Show more
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