Improving stability in two-dimensional transistors with amorphous gate oxides by Fermi-level tuning

Abstract

Electronic devices based on two-dimensional semiconductors suffer from limited electrical stability because charge carriers originating from the semiconductors interact with defects in the surrounding insulators. In field-effect transistors, the resulting trapped charges can lead to large hysteresis and device drifts, particularly when common amorphous gate oxides (such as silicon or hafnium dioxide) are used, hindering stable circuit operation. Here, we show that device stability in graphene-based field-effect transistors with amorphous gate oxides can be improved by Fermi-level tuning. We deliberately tune the Fermi level of the channel to maximize the energy distance between the charge carriers in the channel and the defect bands in the amorphous aluminium gate oxide. Charge trapping is highly sensitive to the energetic alignment of the Fermi level of the channel with the defect band in the insulator, and thus, our approach minimizes the amount of electrically active border traps without the need to reduce the total number of traps in the insulator.

Zero‐Bias Power‐Detector Circuits based on MoS2 Field‐Effect Transistors on Wafer‐Scale Flexible Substrates

“…It is usually an indicator of the presence of border traps which are negatively charged during the sweep in the gate oxide of the transistors. [ 41,50 ] One can observe some substantial differences in the curves other than hysteresis for the M‐material, e.g., a clear degradation of the inverse subthreshold slope (or subthreshold swing, SS) and a reduction of the ON/OFF ratio, compared to the S‐material. This may be attributed to the presence of a higher amount of defects, such as sulfur vacancies, in the multilayer material.…”

Challenges for Nanoscale CMOS Logic Based on Two-Dimensional Materials

“…Furthermore, border traps are characterized by a strong gate bias dependence of these charging time constants, as the defect bands are bent by an applied gate voltage [ 88 ]. In order to improve the electrical stability of 2D FETs, the probability for charge trapping can be considerably reduced if the defect bands in the gate insulator are energetically far away from the conduction and valence band edges of the 2D semiconductor [ 77 ]. For example, n-type WS /HfO FETs are expected to be electrically unstable due to frequent charge trapping events in the electron trapping bands, whereas the stability is likely considerably improved for p-type WS /HfO FETs due to the increased energy barrier for charge trapping, see Figure 4 d. By selecting a suitable combination of 2D semiconductor and gate insulator or by tuning this respective alignment with fixed charges at the interface [ 89 ] or electric dipoles within the gate stack [ 87 ], the number of electrically active charge traps can be minimized.…”

“…( e ) Band diagram of various 2D semiconductors with the three most commonly used amorphous oxides, indicating good stability, for example for black phosphorous (BP) or hafnium disulfide (HfS ) FETs with HfO as a gate insulator. ( d , e ) reproduced from T. Knobloch et al, Nature Electronics 5, 356–366, 2022 [ 77 ].…”

Application of Two-Dimensional Materials towards CMOS-Integrated Gas Sensors

“…Among TMDs, molybdenum disulfide (MoS 2 ) [ 22 , 259 , 263 ] and tungsten sulfide (WS 2 ) [ 264 ] are of particular interest for transistors, since they are naturally occurring layered crystals, are robust and relatively abundant, and present a wide band gap; nevertheless, many other TMDs are also readily being investigated [ 132 , 260 , 265 ]. One of the main issues with 2D TMD semiconductor FETs is finding a fitting insulator, whether in the top-gated or back-gated configuration, where the interface defect concentration is minimal and does not negatively impact transistor operation or its long-term reliability [ 21 , 266 , 267 ]. It should be noted that the back-gated design, shown in Figure 23 for a CVD-grown MoS 2 -based FET is a desirable geometry for sensing applications, since it provides a direct interface between the sensing film and the changing ambient.…”

“…With a focus on chemiresistive sensors, based on semiconductor materials which demonstrate the greatest potential for future CMOS integration and miniaturization, we build on the review we presented at the 32nd International Conference on Microelectronics (MIEL) in 2021 [ 1 ] and summarize some key aspects of currently available gas sensor technologies. Our analysis results in the conclusion that the most likely materials which have the potential for both sensing applications and digital logic are two-dimensional (2D) materials, and we expect this integration in the relatively near future [ 21 , 22 ]. First, we introduce different gas sensing technologies, their integration with CMOS processes, and the current research into room-temperature gas sensing.…”