Controlling the doping level in graphene during integration into silicon CMOS compatible devices is an open challenge. In general, the doping level in graphene is influenced via substrate interactions, metal contacts, and encapsulation layers. Here, we demonstrate a method to control the Fermi level in graphene through transfer onto ionic-doped oxide surfaces. The substrates were prepared to this end by diffusion of ammonia and aluminum on the oxide surface, which induces positive (NSiO+) and negative (AlSiO–) charges on the oxide layer. Van der Pauw measurements show that the charge neutrality or Dirac voltage in graphene can be shifted from about −60 V (n = −8.62 × 1012 cm–2) on standard SiO2 to about 13 V (n = 2.17 × 1012 cm–2) on negatively doped SiO2 layers by manipulating the surface charge. Hall measurements show that the electron mobility in graphene transferred on an as-grown oxide surface is higher than for graphene on a doped oxide because of additional scattering centers. Transfer line method measurements show that the contact resistance between graphene and nickel electrodes varies in average from 683.3 Ω·μm on SiO2 to 1046.6 Ω·μm on negatively doped SiO2 and that it depends on both the substrate surface charge and on graphene sheet resistance. Ionic-doped oxide surfaces are generally temperature-stable with respect to front- and back-end-of-the-line semiconductor manufacturing. The method presented here allows adjustments of the surface charge density of the substrate, and thus in graphene, which cannot be realized by organic or metallic functionalization. Therefore, the method may be suitable for engineering graphene-based devices and circuits, in particular, for applications that require complementary devices or a specific position of the Fermi level in graphene, for example, to adjust contact resistivity, sheet resistance, or sensor sensitivity.
We demonstrate the design, fabrication, and characterization of wafer-scale, zero-bias power detectors based on two-dimensional MoS2 field effect transistors (FETs). The MoS2 FETs are fabricated using a wafer-scale process on 8 µm thick Polyimide film, which in principle serves as flexible substrate. The performances of two CVD-MoS2 sheets, grown with different processes and showing different thicknesses, are analyzed and compared from the single device fabrication and characterization steps to the circuit level. The power detector prototypes exploit the nonlinearity of the transistors above the cut-off frequency of the devices. The proposed detectors are designed employing a transistor model based on measurement results. The fabricated circuits operate in Ku-band between 12 and 18 GHz, with a demonstrated voltage responsivity of 45 V/W at 18 GHz in the case of monolayer MoS2 and 104 V/W at 16 GHz in the case of multilayer MoS2, both achieved without applied DC bias. They are the best performing power detectors fabricated on flexible substrate reported to date. The measured dynamic range exceeds 30 dB outperforming other semiconductor technologies like silicon complementary metal oxide semiconductor (CMOS) circuits and GaAs Schottky diodes.
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