Improved modeling of gate leakage currents for fin–shaped field–effect transistors

Abstract

Articles you may be interested inModel of random telegraph noise in gate-induced drain leakage current of high-k gate dielectric metal-oxidesemiconductor field-effect transistors Appl. Phys. Lett. 100, 033501 (2012); 10.1063/1.3678023 Contribution of carrier tunneling and gate induced drain leakage effects to the gate and drain currents of fin-shaped field-effect transistors J. Appl. Phys. 109, 084524 (2011); 10.1063/1.3575324 Modeling of threshold voltage, mobility, drain current and subthreshold leakage current in virgin and irradiated silicon-on-insulator fin-shaped field effect transistor device J. Appl. Phys. 109, 084504 (2011); 10.1063/1.3553836Modeling of spin metal-oxide-semiconductor field-effect transistor: A nonequilibrium Green's function approach with spin relaxation J. Appl. Phys.Modeling of gate-induced drain leakage current in n-type metal-oxide-semiconductor field effect transistorRecently, we developed a symmetric doped double gate model for MOSFETs, which includes a direct tunneling model for gate current considering its dependence on the voltages applied to the gate and drain electrodes. Since different tunneling mechanisms can dominate the gate and drain/ source leakage currents depending on the transistor operation regime, the gate stack dimensions and the insulating materials used as gate dielectric, in this work, we analyze and model specific features of such currents in SOI FinFET devices. We present an analytical model which takes into account three main conduction mechanisms of leakage currents associated with the gate structure and is valid for a wide operation range. An improved model to describe the behavior of direct tunneling is proposed to avoid the use of fitting parameters. It is shown that carriers tunneling assisted by trap states in the dielectric material of the overlap regions should be considered, as it can become predominant in the subthreshold regime. Moreover, a band-to-band tunneling model is included because of its large impact on the drain leakage current. The present improved model for gate leakage currents is validated by experimental results obtained on FinFETs with different dimensions, gate dielectric materials and performed under different bias conditions. V C 2013 American Institute of Physics. [http://dx.

Gate leakage currents model for FinFETs implemented in Verilog‐A for electronic circuits design

“…The gate leakage currents model for SOI FinFETs was presented in . Thus, the I G component consists of two parts: the current due to direct tunneling (DT) of carriers from the channel region at surface inversion conditions ( I GDT ) and the current that takes place in the overlap regions between drain or source electrodes and the gate.…”

“…In was presented an improved gate current analytical model that considers the dependence on the applied drain (or source) voltage, the free available charge in the Si film, and the physically based parameters of the insulating material, that is, the tunneling barrier height ( φ b ), the electrons mass used for tunneling process ( m i ), the gate dielectric permittivity ( ε i ), and its physical thickness ( t i ). Thereby, an expression for gate current density due to electrons tunneling directly from Si conduction band through the gate dielectric material was established as follows: where q is the electron charge and h is the Planck's constant.…”

“…By considering the dependence of the gate current on drain voltage ( V D ) through the free charge and the applied potential to the Si surface, the empirical correction function is expressed as follows : where V G is the applied gate voltage, V FBc is the flat band voltage corresponding to the channel region, and V def is defined as the effective drain voltage applied to the channel at the saturation point . Finally, the normalized free charge in the Si film ( q g ), which corresponds to the area under control of the gate along the device channel, is expressed as follows : …”

“…Moreover, an improved gate leakage currents model was included in the SDDGM model , which takes into account three main tunneling mechanisms that dominate the leakage currents associated with the gate structure, the most important gate dielectric material parameters, and the applied biases to the MOSFET. This model represents the behavior of the gate leakage current ( I G ) and also its contribution to I D in SOI FinFETs either with single dielectric layer or stacked layers as gate insulator, by the impact of each predominant I G component on the total I D and the contribution of GIDL current ( I GIDL ) to the off‐state leakage current ( I off ).…”

Improved physical models for advanced silicon device processing

“…In addition, the loss of conformality leads to differences in turn-on behavior and current flow on the top and sidewalls of the fin [164] and increased gate-induced drain leakage currents (a major source of off-state leakage in FinFETs) [161,169].…”