Gate leakage currents model for FinFETs implemented in Verilog‐A for electronic circuits design

Abstract

Because different conduction mechanisms can dominate the gate and drain/source leakage currents, mainly depending on the insulating materials used as gate dielectric, the dimensions of the gate structure, and the transistor operation regime, we proposed an improved analytical model to describe the behavior of these currents in silicon on insulator fin-shaped field-effect transistor devices by taking into account changes in the aforementioned factors. This model considers the direct tunneling, trap-assisted tunneling, and band-to-band tunneling as the predominating mechanisms for leakage currents associated with the gate structure. These specific features make the model valid for a wide operation range and include its impact on the drain leakage current. The implementation of this model in Verilog-A code is presented in this work, which allows calculating quickly and accurately the scaling constraint of a specific gate dielectric material and the power consumption that yields such leakage currents in a circuit by using commercial simulators. All presented results are validated with experimental data from fin-shaped field-effect transistors with different dimensions and gate dielectric materials and performed under different bias conditions.

Reducing Off-State and Leakage Currents by Dielectric Permittivity-Graded Stacked Gate Oxides on Trigate FinFETs: A TCAD Study

“…First, we observed that our gate leakage current model is verified as Rudenko [64], Garduno [32], Khan [65], and Golosov [66] have similar trends for IG: starting from a negative VG, IG first decreases significantly around 6-14 orders of magnitude, depending on the gate oxide, takes a minimum at some VG value, and then it increases steeply again.…”

“…Nagy et al [ 31 ] explored nanowire FET architectures through a simulation in a VENDES finite element toolbox that integrated Schrödinger equation-based quantum corrected methods. Garduño [ 32 ] modeled gate leakage currents for many FinFET structures and the implementation was performed in Verilog-A.…”

Analytical model for the drain and gate currents in silicon nanowire and nanosheet MOS transistors valid between 300 and 500 K

“…On the other hand, in reference 25–29, a detailed analysis from the physical point of view was presented for the different components of gate tunneling currents observed in FinFETs. These tunneling currents include: (1) the direct tunneling current through the gate dielectric, along the channel, when the transistor is operating in inversion I G,inv ; (2) the tunneling current through the gate dielectric when the device is in depletion due to charges generated in the channel $$$ {I}_{\mathrm{G},\mathrm{gen}} $$$; (3) the Trap Assisted Tunneling current in the drain overlap region I G,TAT ; (4) the gate‐induced drain leakage current (GIDL) through the overlap region at the drain when the device is in depletion, which is also called transversal GIDL or T‐GIDL, 29 $$$ {I}_{\mathrm{G},\mathrm{T}-\mathrm{GIDL}} $$$.…”