In this paper, we demonstrate that zinc oxide (ZnO) layers deposited by inkjet printing (IJP) can be successfully applied to the low-temperature fabrication of efficient inverted polymer solar cells (i-PSCs).
Articles you may be interested inModel of random telegraph noise in gate-induced drain leakage current of high-k gate dielectric metal-oxidesemiconductor field-effect transistors Appl. Phys. Lett. 100, 033501 (2012); 10.1063/1.3678023 Contribution of carrier tunneling and gate induced drain leakage effects to the gate and drain currents of fin-shaped field-effect transistors J. Appl. Phys. 109, 084524 (2011); 10.1063/1.3575324 Modeling of threshold voltage, mobility, drain current and subthreshold leakage current in virgin and irradiated silicon-on-insulator fin-shaped field effect transistor device J. Appl. Phys. 109, 084504 (2011); 10.1063/1.3553836Modeling of spin metal-oxide-semiconductor field-effect transistor: A nonequilibrium Green's function approach with spin relaxation J. Appl. Phys.Modeling of gate-induced drain leakage current in n-type metal-oxide-semiconductor field effect transistorRecently, we developed a symmetric doped double gate model for MOSFETs, which includes a direct tunneling model for gate current considering its dependence on the voltages applied to the gate and drain electrodes. Since different tunneling mechanisms can dominate the gate and drain/ source leakage currents depending on the transistor operation regime, the gate stack dimensions and the insulating materials used as gate dielectric, in this work, we analyze and model specific features of such currents in SOI FinFET devices. We present an analytical model which takes into account three main conduction mechanisms of leakage currents associated with the gate structure and is valid for a wide operation range. An improved model to describe the behavior of direct tunneling is proposed to avoid the use of fitting parameters. It is shown that carriers tunneling assisted by trap states in the dielectric material of the overlap regions should be considered, as it can become predominant in the subthreshold regime. Moreover, a band-to-band tunneling model is included because of its large impact on the drain leakage current. The present improved model for gate leakage currents is validated by experimental results obtained on FinFETs with different dimensions, gate dielectric materials and performed under different bias conditions. V C 2013 American Institute of Physics. [http://dx.
The temperature dependence in the typical temperature operating range from 300 K up to 370 K of the electrical characteristics of IGZO TFTs fabricated at temperatures not exceeding 200 ºC is presented and modeled. It is seen that up to T=330 K, the transfer curves show a parallel shift toward more negative voltages. In both subthreshold and above threshold regimes, the drain current shows Arrhenius-type dependence. In the latter case, for low temperatures, the activation energy is around 0.35 eV for V GS =10 V, reducing as V GS is increased. The observed behavior is consistent with having the VRH transport mechanism as the predominant one in conduction.
Articles you may be interested inImproved modeling of gate leakage currents for fin-shaped field-effect transistors J. Appl. Phys. 113, 124507 (2013); 10.1063/1.4795403 Model of random telegraph noise in gate-induced drain leakage current of high-k gate dielectric metal-oxidesemiconductor field-effect transistors Appl. Phys. Lett. 100, 033501 (2012); 10.1063/1.3678023 Analytical approach to integrate the different components of direct tunneling current through ultrathin gate oxides in n-channel metal-oxide-semiconductor field-effect transistors Effects of inelastic scattering on direct tunneling gate leakage current in deep submicron metal-oxide-semiconductor transistors J. Appl. Phys. 92, 937 (2002); 10.1063/1.1486022Modeling of gate-induced drain leakage current in n-type metal-oxide-semiconductor field effect transistorThe contribution of carrier tunneling and gate induced drain leakage (GIDL) effects in the total gate and drain currents of FinFET devices with different dimensions is analyzed. In order to fulfill this task, expressions for the leakage current due to carrier tunneling and GIDL effects at a Metal-Dielectric-Semiconductor structure were established and incorporated in the Symmetric Doped Double-Gate Model (SDDGM) for metal-oxide-semiconductor field-effect transistors (MOSFET). It is shown that both phenomena have to be taken into account for precise modeling of the device in all the operation regions although GIDL current can become predominant in the subthreshold region. The dependence of gate tunneling current in inversion and subthreshold regimes of operation is modeled as function of the applied voltages and transistor physical parameters by using analytical expressions. The present leakage current model is validated by comparing modeled with measured total gate and drain currents for FinFETs with different dimensions.
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