Contribution of carrier tunneling and gate induced drain leakage effects to the gate and drain currents of fin–shaped field–effect transistors

Abstract

Articles you may be interested inImproved modeling of gate leakage currents for fin-shaped field-effect transistors J. Appl. Phys. 113, 124507 (2013); 10.1063/1.4795403 Model of random telegraph noise in gate-induced drain leakage current of high-k gate dielectric metal-oxidesemiconductor field-effect transistors Appl. Phys. Lett. 100, 033501 (2012); 10.1063/1.3678023 Analytical approach to integrate the different components of direct tunneling current through ultrathin gate oxides in n-channel metal-oxide-semiconductor field-effect transistors Effects of inelastic scattering on direct tunneling gate leakage current in deep submicron metal-oxide-semiconductor transistors J. Appl. Phys. 92, 937 (2002); 10.1063/1.1486022Modeling of gate-induced drain leakage current in n-type metal-oxide-semiconductor field effect transistorThe contribution of carrier tunneling and gate induced drain leakage (GIDL) effects in the total gate and drain currents of FinFET devices with different dimensions is analyzed. In order to fulfill this task, expressions for the leakage current due to carrier tunneling and GIDL effects at a Metal-Dielectric-Semiconductor structure were established and incorporated in the Symmetric Doped Double-Gate Model (SDDGM) for metal-oxide-semiconductor field-effect transistors (MOSFET). It is shown that both phenomena have to be taken into account for precise modeling of the device in all the operation regions although GIDL current can become predominant in the subthreshold region. The dependence of gate tunneling current in inversion and subthreshold regimes of operation is modeled as function of the applied voltages and transistor physical parameters by using analytical expressions. The present leakage current model is validated by comparing modeled with measured total gate and drain currents for FinFETs with different dimensions.

Improved modeling of gate leakage currents for fin–shaped field–effect transistors

“…Even SOI FinFET structures with high-k gate insulating materials exhibit the presence of DT conduction mechanism. 16 By assuming an independent electron approximation and elastic tunneling process, based on the Wentzel-Kramers-Brillouin (WKB) approximation and using a one-band parabolic dispersion relation for tunneling probability calculation, 13 presented a gate current analytical model with a more physical approach than in Ref. 7.…”

“…The analytic expressions to model the DT effect according to the above operation conditions and the origin of the free charge in the Si body film were described in our previous work. 13 All the corresponding parameters for the current due to DT conduction mechanism associated with generation/recombination processes in the Si body (I Ggen ), under subthreshold conditions and inverse bias of the p-n junction, are summarized in Table II.…”

“…7,8 The leakage current due to gate-induced drain leakage (GIDL) effect in the gate-to-drain overlap region and its contribution to drain current (I D ) is another important issue. [9][10][11][12][13] With the exception of Ref. 13, the presence of I G in the subthreshold region is usually neglected, because its magnitude and impact on I D were lower than those due to GIDL current (I GIDL ).…”

“…[9][10][11][12][13] With the exception of Ref. 13, the presence of I G in the subthreshold region is usually neglected, because its magnitude and impact on I D were lower than those due to GIDL current (I GIDL ).…”

“…13, we presented new analytical expressions to model I G that consider DT through gate dielectric as a function of gate and drain biases, the dielectric physical thickness, electron tunneling effective mass, conduction bandoffset, and the channel geometry, applying it to FinFETs with stacked gate materials.…”