Implementation of optimized high performance 4&amp;#x00D7;4 multiplier using ancient Vedic sutra in 45 nm technology

Kundu, Diptendu Kumar; Srimani, Supriyo; Panda, Saradindu; Maji, Bansibadan

doi:10.1109/icdcsyst.2014.6926192

Cited by 9 publications

(6 citation statements)

References 14 publications

(1 reference statement)

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Today's world demands implementation of techniques which take lesser time and is energy efficient so we have designed a Vedic divider. other researchers have also performed there research work in the field of Vedic mathematics like implementation of 4*4 multiplier using Urdhva-Tiryakbhyam in 45nm technology [8], another division architecture using another Vedic technique known as `Dhwajam' [9]. With the enrichment of new technology there is a huge demand of energy efficiency.…”

Section: Introductionmentioning

confidence: 99%

Capacitance Scaling Based Energy Efficient Vedic Divider using Paravartya Yojayet on 28nm FGPA

Madhok¹,

Goswami²,

Kumar³

2016

GJET

View full text Add to dashboard Cite

In this paper, we have designed an energy efficient Vedic Divider using an ancient Vedic mathematics technique known as "ParavartyaYojayet". Para-vartyaYojayet is a Sanskrit name which means transpose and adjust. Vedic mathematical formulas are used to solve tedious and cumbersome arithmetic operations. Today's world demands implementation of techniques which take lesser time and are energy efficient so we have designed a Vedic divider to solve long divisions in seconds. Our design consists of 2 inputs for dividend and divisor and 2 outputs that are remainder and quotient. Many researchers have done research work on Vedic mathematics to solve DSP operations using Urdhava-Triyagbhayam multiplication sutra, to design asynchronous Vedic DSP processor core and lots more. In our paper we have implemented our code on Xilinx ISE Design Suite 14.2 and results were tested on 28nm FPGA platform. We have done power analysis by varying frequencies and capacitance to make our Vedic divider energy efficient. Analysis results that the maximum power is consumed at 2.2GHz and minimum power is consumed at 1.2GHz. In respect of capacitance maximum power is consumed at 100pF and minimum power is consumed at 20pF.Step 3: We minus divisor 12 from 10 and get -2. Multiply this -2 by first digit of 25 i.e.2 and we finally get -4 and add -4 to 25 and get 21 as quotient as shown in Figure 6. Fig. 7. RTL Schematic of Parvartya Yojayet: Part IIStep 4: Take Mod of 21 and 10 and multiply 1 (i.e.21%10) with -2 and add final result -2 in remainder 4 (in step 1) and final remainder is 2 as shown in Figure 7.

show abstract

Section: Introductionmentioning

confidence: 99%

Capacitance Scaling Based Energy Efficient Vedic Divider using Paravartya Yojayet on 28nm FGPA

Madhok¹,

Goswami²,

Kumar³

2016

GJET

View full text Add to dashboard Cite

show abstract

“…High Speed Transceiver Logic also called HSTL, Stub Series Terminated Logic called SSTL and Transistor-Transistor Logic called TTL are few more IO Standards available on FPGA. Our Energy efficient Vedic multiplier [1][2][3][4][5][6][7][8] design is implemented on 40nm Virtex-6 and 28nm Virtex-7 FPGA. Vedic mathematics deals with a range of Vedic mathematical sutra and their applications to carry out tedious and cumbersome arithmetic operations [2].…”

Section: Introduction Low Voltage Complementary Metal Oxide Semicomentioning

confidence: 99%

“…Vedic mathematics deals with a range of Vedic mathematical sutra and their applications to carry out tedious and cumbersome arithmetic operations [2]. Other researchers have also performed their research work in the field of Vedic mathematics like implementation of 4*4 multiplier using Urdhva-Tiryakbhyam in 45nm technology [3], another division architecture using another Vedic technique ISSN: 2456-0065 DOI: 10.21058/gjet.2015.1202 known as 'Dhwajam' [4]. A design of an 8 bit fixed point, asynchronous Vedic DSP processor core has also been studied [5].…”

Section: Introduction Low Voltage Complementary Metal Oxide Semicomentioning

confidence: 99%

Temperature Sensing Based Energy Efficient Vedic Multiplier Design Using Either Proportionality or Similarity

Gargrish¹,

Pandey²

2015

GJET

View full text Add to dashboard Cite

In this project, an innovative design of energy efficient Vedic Multiplier using a prehistoric Vedic mathematics method known as "Anurupyena Shunyamanyat" have been implemented on FPGA. Anurupyena Shunyamanyat is a Sanskrit name which in simple words means ' proportionality 'or ' similarly '. This Sutra is highly useful to find products of two numbers when both of them are near the frequent bases like 10, 50, 500 etc (multiples of powers of 10). Lesser time and energy efficient is today's world demand. Choice of IO Standard plays a very important role in power indulgence design. So, we have selected most energy efficient IO standard Low Voltage Complementary Metal Oxide Semiconductor also called LVCMOS. Then, we try to achieve more energy efficiency with different technology (40nm and 28nm) based FPGA. Virtex-6 and Kintex-7 are the platforms which have been used in this project. In our paper we have implemented our code on Xilinx ISE Design Suite 14.2 were tested on 28nm and 40nm FPGA. In this project we have observed approx 87-88% decrease in leakage power dissipation when we shift from 40nm to 28nm technology based FPGA.

show abstract

“…A design of an 8 bits fixed point, asynchronous Vedic DSP processor core has also been studied [12]. Implementation of 4*4 multiplier using Urdhva-Tiryakbhyam in 45nm technology [13], another division architecture using different Vedic technique known as `Dhwajam' [14]. Vedic multiplier has been designed earlier using different Vedic formulas but this design using Nikhilam Navatashcaramam Dashatah vedic formula is completely a fresh work and is quite efficient [20][21].In this paper we have designed an energy efficient multiplier that consists of three inputs and one output.…”

Section: Introductionmentioning

confidence: 99%

HSTL IO Standard Based Energy Efficient Multiplier Design using Nikhilam Navatashcaramam Dashatah on 28nm FPGA

Madhok

Pandey

Kaur

et al. 2015

IJCA

View full text Add to dashboard Cite

show abstract

Implementation of optimized high performance 4×4 multiplier using ancient Vedic sutra in 45 nm technology

Cited by 9 publications

References 14 publications

Capacitance Scaling Based Energy Efficient Vedic Divider using Paravartya Yojayet on 28nm FGPA

Capacitance Scaling Based Energy Efficient Vedic Divider using Paravartya Yojayet on 28nm FGPA

Temperature Sensing Based Energy Efficient Vedic Multiplier Design Using Either Proportionality or Similarity

HSTL IO Standard Based Energy Efficient Multiplier Design using Nikhilam Navatashcaramam Dashatah on 28nm FPGA

Contact Info

Product

Resources

About