Impact of STI on Statistical Variability and Reliability of Decananometer MOSFETs

Wang, Xingsheng; Roy, S.; Brown, Andrew R.; Asenov, A.

doi:10.1109/led.2011.2108256

Cited by 16 publications

(9 citation statements)

References 23 publications

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“…The width dependence of LER induced σV T is virtually independent on LER rms but depends on the LER correlation length. Moreover, fringing effects from shallow trench isolation at width ends will additionally modify the width dependence [39]. It is important to note that in extremely scaled bulk MOSFETs both the channel length and the channel width dependence of σV T strongly deviates from the Pelgrom's law.…”

Section: B Channel Widthmentioning

confidence: 99%

Geometry, Temperature, and Body Bias Dependence of Statistical Variability in 20-nm Bulk CMOS Technology: A Comprehensive Simulation Analysis

Wang

Adamu-Lema

Cheng

et al. 2013

IEEE Trans. Electron Devices

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Abstract-Conventional bulk CMOS, which is arguably most vulnerable to statistical variability, has been the workhorse of the electronic industry for more than three decades. In this paper, the dependence of the statistical variability of key figures of merit on gate geometry, temperature and body bias in 25nm gate-length MOSFETs, representative for the 20nm CMOS technology generation, are systematically investigated using 3D statistical simulations. The impact of all relevant sources of statistical variability is taken into account. The geometry dependence of the threshold voltage dispersion (and indeed the dispersion of other key transistor figures of merit) does not necessarily follow the Pelgrom's law due to the complex non-uniform channel doping and the interplay of different statistical-variability sources. The DIBL variation for example follows a log-normal distribution. The temperature significantly affects the magnitudes of threshold-voltage, sub-threshold slope, on/off currents and the corresponding statistical distributions. Reverse body bias increases the threshold voltage and its fluctuation while forward body bias reduces both of them.

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Section: B Channel Widthmentioning

confidence: 99%

Geometry, Temperature, and Body Bias Dependence of Statistical Variability in 20-nm Bulk CMOS Technology: A Comprehensive Simulation Analysis

Wang

Adamu-Lema

Cheng

et al. 2013

IEEE Trans. Electron Devices

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“…The electrical performance of analog Complementary Metal-Oxide-Semiconductor (CMOS) integrated circuits (ICs) is absolutely affected by the layouts of semiconductor devices (dimensions, geometric shape and how they are realized along the silicon wafer) [1][2][3][4][5][6][7][8][9]. Analog electrical performance of CMOS ICs may be also degraded when the devices dimensions are reduced due to the continued evolution of this manufacture process technologies [1][2][3][4][5][6][7][8][9]. The key analog building block used in these CMOS ICs is usually the operational transconductance amplifier (OTA), which is implemented with a differential circuit in its input stage [1][2][3][4][5][6][7][8][9].…”

Section: Introductionmentioning

confidence: 99%

“…Analog electrical performance of CMOS ICs may be also degraded when the devices dimensions are reduced due to the continued evolution of this manufacture process technologies [1][2][3][4][5][6][7][8][9]. The key analog building block used in these CMOS ICs is usually the operational transconductance amplifier (OTA), which is implemented with a differential circuit in its input stage [1][2][3][4][5][6][7][8][9]. The analog electrical performance of the differential circuit crucially depends on how identical or how matched are the devices that compose it, taking into account mainly their dimensions (aspect ratio, W/L, where W and L are respectively the channel width and length) and technological parameters, such as the gate oxide and silicon film thicknesses, and doping concentrations of the drain, channel and source regions, etc.…”

Section: Introductionmentioning

confidence: 99%

Boosting the MOSFETs Matching by Using Diamond Layout Style

Peruzzi

Renaux

Flandre

et al. 2020

JICS

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This manuscript presents an experimental comparative study between the Metal-Oxide-Semiconductor (MOS) Silicon-On-Insulator (SOI) Field Effect Transistors, n-type, (nMOSFETs) matching, which are implemented with the hexagonal gate shape (Diamond) and standard rectangular ones. The main analog parameters and figures of merit of 360 devices are investigated. The results establish that the Diamond SOI MOSFETs with α angles equal to 90o can boost in more than in average -45.8% with a standard deviation of 20.1% the devices matching in comparison to those found with the typical rectangular SOI MOSFETs, concerning the same gate area and bias conditions. Consequently, the Diamond layout style is an alternative technique to reduce the nMOSFETs’ mismatching, considering the analog SOI Complementary MOS (CMOS) integrated circuits (ICs) applications.

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“…It is very difficult to set up an effective robust optimization approach because of the complex thermal loading modes and the complex structure of FBGA assemblies [25], [26].…”

Section: Introductionmentioning

confidence: 99%

Thermal Fatigue Reliability Analysis and Structural Optimization Based on a Robust Method for Microelectronics FBGA Packages

Huang

Pecht

2015

IEEE Trans. Device Mater. Relib.

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In this paper, we propose a mixed robust method based on three-level and second-order experiment design, the quadric surface, and finite-element analysis to analyze and optimize thermal fatigue reliability of an FBGA package. According to structural characteristics of FBGA packages, six design variables are selected as optimized objects. The equivalent thermal fatigue strain of solder joints of FBGA packages is used as an objective function of thermal fatigue reliability optimization design. Threelevel and second-order experiment design was carried out for six design variables, and the equivalent thermal strain of solder joints was calculated by finite-element analysis according to experiment design. Then a quadric surface model of six design variables and the equivalent thermal strain of solder joints was built, and variance analysis and accuracy verification were performed. From the model and significance analysis, the nonlinear relation between design variables and thermal strain of solder joints, and the interaction among design parameters were obtained. Finally, a thermal fatigue robust optimization model was built, and optimum structural parameters and equivalent thermal fatigue strain of solder joints were obtained. Equivalent thermal fatigue strain decreased from 0.01858200 to 0.00951976 and was reduced by 48.77%, as shown by comparing the thermal strains before and after optimization.Index Terms-FBGA package, three-level and second-order experiment design, quadric surface, thermal fatigue reliability, robust optimization design.

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Impact of STI on Statistical Variability and Reliability of Decananometer MOSFETs

Cited by 16 publications

References 23 publications

Geometry, Temperature, and Body Bias Dependence of Statistical Variability in 20-nm Bulk CMOS Technology: A Comprehensive Simulation Analysis

Geometry, Temperature, and Body Bias Dependence of Statistical Variability in 20-nm Bulk CMOS Technology: A Comprehensive Simulation Analysis

Boosting the MOSFETs Matching by Using Diamond Layout Style

Thermal Fatigue Reliability Analysis and Structural Optimization Based on a Robust Method for Microelectronics FBGA Packages

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