Impact of FinFET Technology Introduction in the 3T1D-DRAM Memory Cell

Amat, E.; Almudéver, Carmen G.; Aymerich, Nivard; Canal, Ramón; Rubio, Antonio

doi:10.1109/tdmr.2013.2238542

Cited by 4 publications

(4 citation statements)

References 16 publications

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“…In order to obtain a more realistic working frequency value, we simulate 2kB memory blocks based on 3T1D cells. To do this, the circuit is evaluated with a reconfigurable array of 32 cells per column, 512 columns and 24 redundant columns following [21]. So, Fig.…”

Section: Relevance Of the Device Type On Edram Behaviormentioning

confidence: 99%

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Feasibility of Embedded DRAM Cells on FinFET Technology

Amat

Calomarde

Moll

et al. 2016

IEEE Trans. Comput.

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In this work, we analyze the suitability to implement embedded DRAM (eDRAM) cells on FinFET technology and we compare it to classical planar MOSFETs. The results show a significant improvement in the overall cell performance for multi-gate devices. While pMOS FinFET-based memories present better cell behavior and variability robustness, n/pMOS mixed cells show the highest working frequency and a negligible impact on degradation. Finally, we show that using a multiple fin-height strategy, we can reduce (>10%) the layout area of the eDRAM cells.

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Section: Relevance Of the Device Type On Edram Behaviormentioning

confidence: 99%

“…In this sense, an efficient proposal is a mixed n/pMOS (asymmetric) cell, [15]. Although the impact of the FinFET introduction has been extensively investigated in the case of SRAM cells [2,7,9], few studies can be found for eDRAM [21]. The objective of this paper is to contribute to characterize eDRAMs cells based on FinFET technology.…”

Section: Introductionmentioning

confidence: 99%

Feasibility of Embedded DRAM Cells on FinFET Technology

Amat

Calomarde

Moll

et al. 2016

IEEE Trans. Comput.

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“…11 Several studies are conducted to analyze Predictive Technology Models (PTM) 12 based circuits with technology scaling. [13][14][15][16] For instance, a simulation study for PTM ring oscillator and some basic logic gates is discussed. 13 In this work, we evaluate the performance of FinFET-based FPGA cluster and the components comprising it with technology scaling from 20 nm down to 7 nm.…”

Section: Introductionmentioning

confidence: 99%

Technology Scaling Roadmap for FinFET-Based FPGA Clusters Under Process Variations

Abdelkader

El-Din

Mostafa

et al. 2017

J CIRCUIT SYST COMP

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The technology scaling impact on FinFET-based Field-Programmable Gate Array (FPGA) components (Flip-Flops and Multiplexers) and cluster metrics is evaluated for technology nodes starting from 20[Formula: see text]nm down to 7[Formula: see text]nm. Power consumption, delay and energy (Power Delay Product, or PDP) trends are reported with FinFET technology scaling. Cluster metrics are then evaluated based on three benchmarking circuits: 2-bit adder, 4-bit NAND and cascaded flip-flops chain. The study shows that power, delay and PDP of the FPGA cluster are improved as we scale down the technology. An example for improvement is that for 7[Formula: see text]nm 2-bit adder, circuit speed is 15% higher than its value at 20[Formula: see text]nm and PDP at 7[Formula: see text]nm is reduced by 43% compared to its value at 20[Formula: see text]nm. The impacts of temperature and threshold voltage variations on FPGA cluster performance are also reported after evaluating a 2-bit adder circuit as a benchmark which is then used to calculate the design constraints to meet 99.9% yield percentage.

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“…Some studies have discussed analysis of predictive technology models (PTM) circuits with technology scaling [10][11][12][13]. For instance, a simulation study for PTM ring oscillator and basic logic gates is discussed [10].…”

Section: Introductionmentioning

confidence: 99%

Impact of technology scaling on the minimum energy point for FinFET based flip-flops

Abdelkader

Mostafa

Abdelhamid

et al. 2015

2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS)

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Analysis of FinFET based transmission gate (TG), sense amplifier (SA), and semi dynamic (SD) Flip-flops metrics are evaluated with technology scaling from 20nm down to 7nm technology node. The impact of supply voltage variation on delay, power, and energy is reported. The power delay product of Flip-flops is enhanced with technology scaling. The optimum supply voltage value at each technology node from minimum energy perspective is evaluated which is used by the industry to optimize logic and memory circuitry designs. For instance, considering the 7nm TG Flip-flop, the optimum supply voltage from energy saving point of view occurs at 0.65V. The work also characterizes each Flip-flop according to the obtained simulation results. SD Flip-flop has the best performance, however it exhibits high power consumption. TG Flip-flop is the best choice from power dissipation perspective, but it has high clock load. SA Flip-flop has a very useful feature of monotonous transitions at the outputs, which drives fast domino logic, however it might have glitches and it is the most vulnerable to soft errors.

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Impact of FinFET Technology Introduction in the 3T1D-DRAM Memory Cell

Cited by 4 publications

References 16 publications

Feasibility of Embedded DRAM Cells on FinFET Technology

Feasibility of Embedded DRAM Cells on FinFET Technology

Technology Scaling Roadmap for FinFET-Based FPGA Clusters Under Process Variations

Impact of technology scaling on the minimum energy point for FinFET based flip-flops

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