No abstract

No abstract

It has been stated that 3T1D-DRAM cell is a valid alternative to be implemented on L1 memory cache to substitute 6T, highly affected by variability. In this paper, it is shown that the 3T1D memory cells present significant tolerance to high levels of device parameter fluctuation when they are scaled to nodes smaller than 22 nm. Furthermore, we present some strategies to mitigate the cell variability. Moreover, while scaling down capacitorless DRAM cells is a challenging trend, we also show how the scaling drawbacks can be compensated through the following: 1) the channel strain of the cell devices and 2) the proposal of new strategies to further enhance the memory cell behavior.

a b s t r a c tThis paper studies the device variability influence on 6T-SRAM cells in a function of the regularity level of their layout. Systematic and random variations have been analyzed when these memory circuits are implemented on a 45 nm technology node. The NBTI aging relevance on these cells has been also studied for two layout topologies and SNM has been seen as the parameter that suffers the highest impact with respect to cell aging and variability.

No abstract