Technology Scaling Roadmap for FinFET-Based FPGA Clusters Under Process Variations

Abdelkader, Osama; El-Din, Mohamed Mohie; Mostafa, Hassan; Abdelhamid, Hamdy; Fahmy, H. M.; Ismail, Yehea; Soliman, Ahmed M.

doi:10.1142/s0218126618500561

Cited by 7 publications

(5 citation statements)

References 18 publications

(30 reference statements)

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“…To compare with a 7 nm CMOS 2-bit, which can be built with 3 AND gates, 1 OR gate, and 3 XOR gates we make use of the energy, delay, and area estimates in 79 .…”

Section: Performance Evaluation and Discussionmentioning

confidence: 99%

Non-Binary Spin Wave Based Circuit Design

Mahmoud

Vanderveken

Ciubotaru

et al. 2022

IEEE Trans. Circuits Syst. I

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By their very nature, Spin Waves (SWs) excited at the same frequency but different amplitudes, propagate through waveguides and interfere with each other at the expense of ultra-low energy consumption. In addition, all (part) of the SW energy can be moved from one waveguide to another by means of coupling effects. In this paper we make use of these SW features and introduce a novel non Boolean algebra based paradigm, which enables domain conversion free ultra-low energy consumption SW based computing. Subsequently, we leverage this computing paradigm by designing a non-binary spin wave adder, which we validate by means of micro-magnetic simulation. To get more inside on the proposed adder potential we assume a 2-bit adder implementation as discussion vehicle, evaluate its area, delay, and energy consumption, and compare it with conventional SW and 7 nm CMOS counterparts. The results indicate that our proposal diminishes the energy consumption by a factor of 3.14x and 6x, when compared with the conventional SW and 7 nm CMOS functionally equivalent designs, respectively. Furthermore, the proposed non-binary adder implementation requires the least number of devices, which indicates its potential for small chip real-estate realizations.

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“…To compare with a 7 nm CMOS 2-bit, which can be built with 3 AND gates, 1 OR gate, and 3 XOR gates we make use of the energy, delay, and area estimates in 79 .…”

Section: Performance Evaluation and Discussionmentioning

confidence: 99%

Non-Binary Spin Wave Based Circuit Design

Mahmoud

Vanderveken

Ciubotaru

et al. 2022

IEEE Trans. Circuits Syst. I

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“…If n no. of identical fins are connected in parallel, the effective channel width is given by

W_{eff} = normaln . ((), {2H}_{fin} + t_{si}) .

The effective length of the channel in FinFET is given by

L_{total} = L_{gw} + 2 . L_{finext},

where L gw is the length of the gate covering the fin and L finext is the length of the fin on two sides connecting source and drain.…”

Section: Introductionmentioning

confidence: 99%

“…Scaling of devices leads to an increase in leakage currents due to unwanted short channel effects . These short channel effects can be reduced by using multi‐gate field‐effect transistor (FET) . This multi‐gate FET is termed as fin field‐effect transistor (FinFET).…”

Section: Introductionmentioning

confidence: 99%

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FDSTDL: Low‐power technique for FinFET domino circuits

Garg

Gupta

2019

Circuit Theory & Apps

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Summary Major issues in designing low‐power high‐speed VLSI circuits are propagation delay, power consumption, and noise tolerance. This paper describes fin field‐effect transistor (FinFET) technology for the design of low‐power VLSI circuits. FinFET uses two gates (front and back) in place of a single gate as in complementary metal‐oxide–semiconductor (CMOS) technology for better control of the channel. A new technique foot driven stack transistor domino logic (FDSTDL) is proposed for designing domino logic circuits in order to reduce leakage power and propagation delay. In this paper, 2‐, 4‐, 8‐, and 16‐input domino OR gates are designed and simulated using existing and proposed techniques in CMOS and FinFET technology. Simulation is done on the 32 nm predictive technology model (PTM) node using HSPICE on a direct current (DC) supply voltage of 0.9 V. The proposed circuit is simulated in two modes of FinFET, short gate (SG) mode, and low power (LP) mode. The proposed technique shows maximum power reduction of 43.45% in SG mode in comparison with conditional stacked keeper domino logic (CSK‐DL) technique and maximum delay reduction of 38.66% in LP mode in comparison with coarse‐mesh finite difference (CMFD) technique at a frequency of 200 MHz.

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“…The tiny size of the MOSFET, less than tens of nanometers, created some operational problems such as high sub-threshold conduction which means; in the MOSFET, the applied voltage to gate terminal is to be decreased to maintain the reliability [2]- [3]. Then the threshold voltage which is to be applied to the MOSFET must also be reduced.…”

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confidence: 99%

Design and Performance Evaluation of Energy Efficient 8-Bit ALU At Ultra Low Supply Voltages Using FinFET With 20nm Technology

Vijay¹,

Shaik

Shekar³

et al. 2020

International Journal of Systems Applications, Engineering &Amp; Development

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ince last few years, the tiny size of MOSFET, that is less than tens of nanometers, created some operational problems such as increased gate-oxide leakage, amplified junction leakage, high sub-threshold conduction, and reduced output resistance. To overcome the above challenges, FinFET has the advantages of an increase in the operating speed, reduced power consumption, decreased static leakage current is used to realize the majority of the applications by replacing MOSFET. By considering the attractive features of the FinFET, an ALU is designed as an application. In the digital processor, the arithmetic and logical operations are executed using the Arithmetic logic unit (ALU). In this paper, power efficient 8-bit ALU is designed with Full adder (FA) and multiplexers composed of Gate diffusion input (GDI) which gained designer's choice for digital combinational circuit realization at minimum power consumption. The design is simulated using Cadence virtuoso with 20nm technology. Comparative performance analysis is carried out in contrast to the other standard circuits by taking the critical performance metrics such as delay, power, and power delay product (PDP), energy-delay product (EDP) metrics into consideration.

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Technology Scaling Roadmap for FinFET-Based FPGA Clusters Under Process Variations

Cited by 7 publications

References 18 publications

Non-Binary Spin Wave Based Circuit Design

Non-Binary Spin Wave Based Circuit Design

FDSTDL: Low‐power technique for FinFET domino circuits

Design and Performance Evaluation of Energy Efficient 8-Bit ALU At Ultra Low Supply Voltages Using FinFET With 20nm Technology

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