FDSTDL: Low‐power technique for FinFET domino circuits

Garg, Sandeep; Gupta, Tarun Kumar

doi:10.1002/cta.2627

Cited by 24 publications

(12 citation statements)

References 29 publications

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“…This amplitude of noise pulse obtained at the output is equal to the UNG of the circuit. UNG is given by 30,[32][33][34][35][36] : Figure 17 and 18 shows that proposed (DCHSDL) technique has greater UNG for 2, 4, 8 and 16 input OR gates in comparison with existing domino techniques in CMOS and CNFET technologies. Proposed technique shows an improvement of 1.05× to 1.63× in UNG in comparison with various existing techniques.…”

Section: Resultsmentioning

confidence: 97%

“…The contention between PDN and keeper increases with the increase in the size of the keeper which, in turn, increases power consumption and delay of the circuit. 29,30 A current mirror transistor NM 3 is connected in parallel for reducing delay. 28 A footer n-channel CNFET is connected between the evaluation network and ground, due to that leakage current in FLDL circuit is decreases.…”

Section: Domino Circuitsmentioning

confidence: 99%

“…Therefore, it is called Current Mirror Footed Domino Logic (CMFD). 29,30 A current mirror transistor NM 3 is connected in parallel for reducing delay.…”

Section: Domino Circuitsmentioning

confidence: 99%

“…Therefore, the noise immunity of the circuit decreases and robustness of the circuit improves. This technique is termed as Conditional Stacked keeper Domino Logic F I G U R E 6 Current Mirror footed domino (CMFD) 29,30 F I G U R E 7 High-speed clocked delay domino logic (HSCD) 29,31 (CSK-DL) shown in Figure 10. The major disadvantage of this technique is the area of the circuit due to large number of transistors.…”

Section: F I G U R E 5 Footed Domino Logic (Fdl) 22mentioning

confidence: 99%

“…The voltages at node A and B control the currents I 1 and I 2 respectively. When all inputs to the evaluation logic becomes low, the voltage at node A becomes 29,30 greater than the voltage at node B. Therefore, I 1 will be greater than I 2 , otherwise, if any of the inputs in OR gate becomes high, the current flow through PDN and output becomes high..…”

Section: F I G U R E 5 Footed Domino Logic (Fdl) 22mentioning

confidence: 99%

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A 1‐bit full adder using CNFET based dual chirality high speed domino logic

Garg

Gupta

Pandey³

2019

Circuit Theory & Apps

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CNFET devices are preferred over CMOS devices for designing high-speed digital circuits. This paper introduces a new technique Dual Chirality High-speed Domino Logic (DCHSDL) for implementing low power and high-speed domino circuits in CNFET technology. Simulations are carried out for 32 nm Stanford CNFET model in HSPICE for 2, 4, 8 and 16 input domino OR gates at a clock frequency of 200 MHz on a DC supply voltage of 0.9 V. The proposed domino technique shows maximum power reduction of 82.55% and maximum delay reduction of 57.97% compared to CPVT technique in CNFET technology at a frequency of 200 MHz. The proposed circuit shows maximum power reduction of 97.90% compared to its analogous circuit in CMOS technology for a 2-input domino OR gate. The proposed technique shows maximum improvement of 1.05× to 1.63× in unity noise gain (UNG) compared to various existing techniques in CNFET technology at a frequency of 200 MHz. The 1-bit Full Adderdesigned using the proposed technique shows a power reduction of 16.91% and a delay reduction of 23.64% compared to standard FDL 1-bit Full Adder. K E Y W O R D SCNFET, Domino, Dynamic, FOM, VLSI

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Section: Resultsmentioning

confidence: 97%

Section: Domino Circuitsmentioning

confidence: 99%

“…Therefore, it is called Current Mirror Footed Domino Logic (CMFD). 29,30 A current mirror transistor NM 3 is connected in parallel for reducing delay.…”

Section: Domino Circuitsmentioning

confidence: 99%

Section: F I G U R E 5 Footed Domino Logic (Fdl) 22mentioning

confidence: 99%

Section: F I G U R E 5 Footed Domino Logic (Fdl) 22mentioning

confidence: 99%

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A 1‐bit full adder using CNFET based dual chirality high speed domino logic

Garg

Gupta

Pandey³

2019

Circuit Theory & Apps

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Ultrafast and Ultralow‐Power Voltage‐Dominated Magnetic Logic

Mou

et al. 2022

Advanced Intelligent Systems

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Conventional computers are built on devices combining a volatile silicon-based complementary metalÀoxideÀsemiconductor (CMOS) logic processor with external nonvolatile memory. Frequent communication between the logic processor and the memory results in low speed and high power consumption [1] (the von Neumann performance bottleneck). A promising approach to address this issue is combining reconfigurable logic and built-in nonvolatile memory through the use of magnetic logic [2] , such as magnetic field-controlled logic, [3] electric field-controlled magnetic logic, [4][5][6][7] magnetic domainwall (DW) logic, [8][9][10][11] magnetic logic based on magnetic tunnel junctions (MTJs), [12,13] or the anomalous Hall effect (AHE). [14,15] All of these approaches, however, suffer from certain limitations.Diode-assisted geometry-enhanced low-magnetic-field magnetoresistance in silicon can be used to perform basic Boolean logic operations. The large required magnetic field (0.15 T) limits, however, application of this approach. Magnetic switching can also be controlled using a ferromagnetic/ferroelectric structure [5] or electrical gating of the oxygen level, [7] forming electric field-controlled magnetic logic. However, the long times and limited suitability for cascading also make this approach unsuitable for practical applications. [6,16] Magnetic DW logic-encoded data and processed logic or memristive operations with DWs propagating through complex networks of nanowires under the action of an externally applied magnetic field or current have also been investigated. [8,10] For magnetic logic based on MTJs and Schottky diode-enhanced MTJs, basic logic and arithmetic operations have also been implemented. [3,12,13] However, the power demand for magnetic DW logic and MTJbased logic is determined by the critical current for magnetic switching, as the current in the logic operation is used to drive directly magnetic switching. A DW logic of 1 μm in size has switching time of 6.25 ns and power consumption of 20.4 pJ, [10] while magnetic logic based on a 40 nm MTJ has a switching time of 1.31 ns and power consumption of 49.6 pJ. [17] Luo et. al proposed a form of magnetic logic by coupling the AHE and current-controlled negative differential resistance, thereby realizing in-memory computing. [15] This device has a long switching time of %100 ns, arising from the internal turn-on properties of current-controlled negative differential resisitance. To address this problem, Pu et. al replaced the current-controlled negative differential resisitance with insulator-to-metal transition materials, thereby achieving a reduction in switching time to 7.5 ns. [14] However, in these devices, the logic output is in the form of the current, and as such it is difficult to perform complex logic operations via cascading. In addition, as the turn-on resistance of current-controlled negative resistance components is large, and the current required for logic operations is large, the switching time is still relatively long, and the power consu...

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An improved charge‐sharing elimination pseudo‐domino logic

Ghimiray

Meher

Dutta

2020

Circuit Theory & Apps

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SummaryIn low‐power digital circuit, the deviation of node voltage from nominal value due to charge‐sharing leads to erroneous output. This problem is more prominent in domino logic when the device is scaled down. The scaling of the device involves scaling of threshold voltage, resulting in high leakage, less robustness and degradation in noise margin. The paper proposes an improved domino approach in terms of reduced leakage, low power dissipation and better noise margin. The stacking effect and pseudo buffer are used in precharge phase to control the gate‐to‐source voltage of pull‐down network for less power consumption and increase in performance in terms of speed of operation. A modified keeper is introduced to reduce the charge‐sharing problem. The proposed domino approach is tested against area overhead, ageing and process, voltage and temperature variation. The circuit is simulated using Cadence Virtuoso Spectre for 90 nm technology. The results obtained from the simulation represent the usefulness of the proposed circuit in terms of power dissipation, stability due to temperature variation, leakage due to temperature variation and delay. The result also shows that the circuit is less prone to charge redistribution problem that exist in domino circuit.

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FDSTDL: Low‐power technique for FinFET domino circuits

Cited by 24 publications

References 29 publications

A 1‐bit full adder using CNFET based dual chirality high speed domino logic

A 1‐bit full adder using CNFET based dual chirality high speed domino logic

Ultrafast and Ultralow‐Power Voltage‐Dominated Magnetic Logic

An improved charge‐sharing elimination pseudo‐domino logic

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