Impact of buffer leakage on intrinsic reliability of 650V AlGaN/GaN HEMTs

Moens, P.; Banerjee, Abhishek; Uren, Michael J.; Meneghini, Matteo; Karboyan, Serge; Chatterjee, Indranil; Vanmeerbeek, P.; Cäsar, Markus; Liu, C.; Salih, Ali; Zanoni, Enrico; Meneghesso, Gaudenzio; Kuball, Martin; Tack, M.

doi:10.1109/iedm.2015.7409831

Cited by 51 publications

(42 citation statements)

References 6 publications

(13 reference statements)

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“…V TFL is the voltage at which the traps in the buffer are ionized, so the quasi-Fermi level is de-pinned and moves up to the band-edge, hence the steep increase in current with voltage (J~V n behavior). The traps are identified using current DLTS as C-atoms on an N-site at E v +0.85eV (8,9). Above V TFL , the vertical field becomes large enough to stimulate field-enhanced Poole-Frenkel current conduction (9,11) which allows the charge in the C N acceptors to leak away.…”

Section: Leakage and Charge Storage In The Buffer Structurementioning

confidence: 99%

“…The importance of the buffer epi stack for off-state stress of 600V GaN-on-Si devices is discussed in (7), but without re-porting any voltage acceleration data or model. In (8), the role of space charge limited (SCL) buffer current in the dyn Ron and degradation under HTRB stress is discussed. However, no voltage-accelerated degradation under HTRB stress between 420V and 850V is observed, which is explained by the GaN buffer stack becoming resistive above a certain critical voltage (trap filling level V TFL ), allowing the trapped charge to leak away.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

(Invited) Intrinsic Reliability Assessment of 650V Rated AlGaN/GaN Based Power Devices: An Industry Perspective

Moens¹,

Banerjee²,

Constant³

et al. 2016

ECS Trans.

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Section: Leakage and Charge Storage In The Buffer Structurementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

(Invited) Intrinsic Reliability Assessment of 650V Rated AlGaN/GaN Based Power Devices: An Industry Perspective

Moens¹,

Banerjee²,

Constant³

et al. 2016

ECS Trans.

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“…As in the case of normally-off transistors, the exposure to high drain bias in the off-state can trigger further trapping processes, due to the filling of surface states [8], to defects located in the (Cdoped) buffer [6], or to the injection of electrons from the substrate [38]. These trapping processes are not specific for p-GaN gate devices, and their discussion is beyond the scope of this paper.…”

Section: Charge Trapping Processes Related To the P-gan Gatementioning

confidence: 97%

“…When the transistor is in the off-state (condition (1) in Figure 1), a high drain-source voltage is applied to the HEMT. The high resulting field ( Figure 2) may favor charge trapping mechanisms, including the filling/depletion of defects located in the C-doped buffer [6], the injection of electrons from the substrate [7], and surface trapping processes [8]. These mechanisms are typically fully recoverable.…”

Section: Introductionmentioning

confidence: 99%

Technology and Reliability of Normally-Off GaN HEMTs with p-Type Gate

et al. 2017

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Abstract:GaN-based transistors with p-GaN gate are commonly accepted as promising devices for application in power converters, thanks to the positive and stable threshold voltage, the low on-resistance and the high breakdown field. This paper reviews the most recent results on the technology and reliability of these devices by presenting original data. The first part of the paper describes the technological issues related to the development of a p-GaN gate, and the most promising solutions for minimizing the gate leakage current. In the second part of the paper, we describe the most relevant mechanisms that limit the dynamic performance and the reliability of GaN-based normally-off transistors. More specifically, we discuss the following aspects: (i) the trapping effects specific for the p-GaN gate; (ii) the time-dependent breakdown of the p-GaN gate during positive gate stress and the related physics of failure; (iii) the stability of the electrical parameters during operation at high drain voltages. The results presented within this paper provide information on the current status of the performance and reliability of GaN-based E-mode transistors, and on the related technological issues.

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“…They were biased in the off-state with V GS = −7V and V DS = 100V for a time period of 1000s before pulsing to the on-state with V GS = 0V, V DS = 1V. This corresponds to a "worst case" V DS for dynamic R ON measurement [23,24]. The on-state current, I DON , was then recorded for 1000s allowing the device to return towards equilibrium.…”

Section: Methodsmentioning

confidence: 99%