IBM power5 chip: a dual-core multithreaded processor

Kalla, R.; Sinharoy, Balaram; Tendler, Joel M.

doi:10.1109/mm.2004.1289290

Cited by 282 publications

(173 citation statements)

References 4 publications

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“…We evaluate our techniques in the context of the IBM Power5+ [20]. The Power5+ has one memory controllerwith an AHB memory scheduler-and two processors per chip, where each processor supports two SMT threads.…”

Section: Simulated Systemmentioning

confidence: 99%

A comprehensive approach to DRAM power management

Hur¹,

Lin

2008

2008 IEEE 14th International Symposium on High Performance Computer Architecture

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Section: Simulated Systemmentioning

confidence: 99%

A comprehensive approach to DRAM power management

Hur¹,

Lin

2008

2008 IEEE 14th International Symposium on High Performance Computer Architecture

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“…deliver processors providing multithreading capabilities, that is, they provide support to run several threads simultaneously. Some examples of current multithreaded processors are Intel's Montecito [14] and IBM Power 5 [10]. Also, leading manufacturers of the embedded sector, like ARM, plan to include multithreading technology in next-generation processors [16].…”

Section: Introductionmentioning

confidence: 99%

A Dynamic Power-Aware Partitioner with Task Migration for Multicore Embedded Systems

March

Sahuquillo

Petit

et al. 2011

Euro-Par 2011 Parallel Processing

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Abstract. Nowadays, a key design issue in embedded systems is how to reduce the power consumption, since batteries have a limited energy budget. For this purpose, several techniques such as Dynamic Voltage Scaling (DVS) or task migration can be used. DVS allows reducing power by selecting the optimal voltage supply, while task migration achieves this effect by balancing the workload among cores. This paper first analyzes the impact on energy due to task migration in multicore embedded systems with DVS capability and using the well-known Worst Fit (WF) partitioning heuristic. To reduce overhead, migrations are only performed at the time that a task arrives to and/or leaves the system and, in such a case, only one migration is allowed. The huge potential on energy saving due to task migration, leads us to propose a new dynamic partitioner, namely DP, that migrates tasks in a more efficient way than typical partitioners. Unlike WF, the proposed algorithm examines which is the optimal target core before allowing a migration. Experimental results show that DP can improve energy consumption in a factor up to 2.74 over the typical WF algorithm.

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“…To estimate system-level metrics, we leveraged the SESC [2] simulation tool, a fast MIPS instruction set simulator for CMPs providing dynamic energy and execution cycles measures associated to the execution of the target application. Area estimation has been carried out by using the models proposed in [3]. Although in this paper the SESC simulator has been used, the proposed framework is more general and easily retargetable to other multi-processor architectures and technology nodes.…”

Section: Introductionmentioning

confidence: 99%

Variability-aware robust design space exploration of chip multiprocessor architectures

Palermo¹,

Silvano²,

Zaccaria³

2009

2009 Asia and South Pacific Design Automation Conference

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Abstract-In the context of a design space exploration framework for supporting the platform-based design approach, we address the problem of robustness with respect to manufacturing process variations. First, we introduce response surface modeling techniques to enable an efficient evaluation of the statistical measures of execution time and energy consumption for each system configuration. We then introduce a robust design space exploration framework to afford the problem of the impact of manufacturing process variations onto the system-level metrics and consequently onto the application-level constraints. We finally provide a comparison of our design space exploration technique with conventional approaches. 1 I. INTRODUCTION Process variation is dramatically becoming one of the most important challenges related to power and performance optimization for sub-90 nm CMOS technologies. Parametric yield, i.e., the percentage of dies that meet power and performance constraints, has become as important as power and performance optimization itself.Manufacturing process variability is mainly due to inter-die and intra-die variations. Inter and intra-die variations affect low level process parameters such as the channel gate length, the thickness of the oxide and the threshold voltage, which, in turn, affect the critical path delay and static and dynamic power consumption. Inter-die fluctuations affect uniformly every element on a die and consist of lot-to-lot and wafer-towafer variations such as processing temperatures, equipment properties, wafer polishing, wafer placement and the resist thickness. Conversely, intra-die parameter fluctuations consist of both random and systematic components and generate nonuniform electrical characteristics across the chip [1].In this scenario, we address the problem of variabilityaware design at system-level for chip multi-processors (CMP). More precisely, we tackle the problem of the impact of manufacturing process variations onto the system-level metrics and consequently onto the application-level constraints.The main contribution of this paper is twofold:• We introduce a design space exploration (DSE) framework which is robust with respect to manufacturing process variations. The main goal is the optimization of the dispersion of the target system metrics and the maximization of the yield of the system with respect to the application-level constraints.• The exploration process is supported by response surface modeling (RSM) techniques for improving the overall estimation time to obtain the system-level metrics associated to each system configuration. The DSE framework is based on a set of state-of-the-art accurate performance, area and energy models of a CMP

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IBM power5 chip: a dual-core multithreaded processor

Cited by 282 publications

References 4 publications

A comprehensive approach to DRAM power management

A comprehensive approach to DRAM power management

A Dynamic Power-Aware Partitioner with Task Migration for Multicore Embedded Systems

Variability-aware robust design space exploration of chip multiprocessor architectures

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