A comprehensive approach to DRAM power management

Hur, Ibrahim; Lin, Calvin

doi:10.1109/hpca.2008.4658648

Cited by 98 publications

(69 citation statements)

References 28 publications

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“…A rank switches to PD slow exit immediately after the request queue for that rank becomes empty, as proposed in [17]. If the rank remains idle for a time period equal to t REFI , then the rank switches to SR mode.…”

Section: Simulation Methodologymentioning

confidence: 99%

Coordinated refresh: Energy efficient techniques for DRAM refresh scheduling

Bhati

Chishti

Jacob

2013

International Symposium on Low Power Electronics and Design (ISLPED)

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Abstract-As the size and speed of DRAM devices increase, the performance and energy overheads due to refresh become more significant. To reduce refresh penalty we propose techniques referred collectively as "Coordinated Refresh", in which scheduling of low power modes and refresh commands are coordinated so that most of the required refreshes are issued when the DRAM device is in the deepest low power Self Refresh (SR) mode. Our approach saves DRAM background power because the peripheral circuitry and clocks are turned off in the SR mode. Our proposed solutions improve DRAM energy efficiency by 10% as compared to baseline, averaged across all the SPEC CPU 2006 benchmarks.

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Section: Simulation Methodologymentioning

confidence: 99%

Coordinated refresh: Energy efficient techniques for DRAM refresh scheduling

Bhati

Chishti

Jacob

2013

International Symposium on Low Power Electronics and Design (ISLPED)

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“…Token-Based Adaptive Power Gating (TAP) [13], a technique to power gating the cores during memory accesses, TAP works by observing and predicting the system memory request power gate the core without performance or energy loss. A mixed approach for the same goal is presented in [2] the literature describe a simple power down policy for exploiting low power modes of DRAMs, with adaptive history-based memory schedulers and throttling approach that arbitrarily reduces DRAM activity by delaying the issuance of memory commands.…”

Section: Literature Reviewmentioning

confidence: 99%

An Efficient DRAM with Reduced Energy Consumption in Video Driver

Khan¹,

Beohar²,

Gurjar³

2014

IJCA

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Power reduction in electronic and computing system is one of the basic requirements and is increasingly demanded for the battery operated mobile systems. Although the power is required for every part of the system but the devices accessed most frequently (processor, DRAM) are takes special attention, because the improvement in power dissipation in these devices can dramatically reduce the overall power requirement. Since the many approaches have been already proposed for the power reduction in processor this paper focuses on the power reduction in DRAM. The DRAM may be considered as most power consuming device after processor, even when it is idle. Although the DRAMs inherently supports different power saving modes, like selfrefresh and power-down, but these techniques are not as efficient and also causes the unwanted delay which in noncomprisable for the many multimedia applications. Hence in this paper, we propose and evaluate an efficient DRAM rank grouping and power gating technique for power-saving that optimizes the power saving with marginal performance degradation. The proposed approach is developed and tested on several multimedia operations and the experimental results show that it reduces the total DRAM energy consumption between 56% and 183%(approx)at a negligible performance penalty between 3% and 5%(approx).

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“…Existing techniques usually manage power for the main memory by passively monitoring the memory traffic and regulation. Some algorithms are proposed to predict when to power down which memory units and into which low-power state to transition [12,13]. In large scale data centers, server systems, or in the enterprise storage system, power consumption of hard disks is a critical issue where data-intensive applications exhaust disk storage extensively.…”

Section: Related Workmentioning

confidence: 99%

Online Power Measurement and Prediction of PCs

Jiang

Zhao

2010

AMR

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Abstract. Since more power consumption results in more failures and degradations in system performance, reliability, and power bills, it has been a critical problem for not only large scale server system but also personal computers (PCs). Though much literature has focused on energy management and power budgeting for server systems, power consumption of PCs does not attain sufficient attentions fairly. In this paper an online power measurement and prediction framework is proposed and used to save more energy considering the PC as a whole controlled system. The framework includes parts such as power measurement unit, power prediction unit and a simple execution unit of power reduction decisions. A hardware-software joint prototype is implemented based on an intelligent digital multimeter. Experiments on a desktop PC and a laptop show that PC with the framework can save more power consumptions than that of the PCs without this framework.

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A comprehensive approach to DRAM power management

Abstract: Abstract

Cited by 98 publications

References 28 publications

Coordinated refresh: Energy efficient techniques for DRAM refresh scheduling

Coordinated refresh: Energy efficient techniques for DRAM refresh scheduling

An Efficient DRAM with Reduced Energy Consumption in Video Driver

Online Power Measurement and Prediction of PCs

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